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2,077 Commits 22 Branches 25 Tags
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Commit Graph
1302 Commits
Author SHA1 Message Date
Gwenhael Goavec-Merou a2d8bc861f Merge pull request #437 from UweBonnes/xc6v 
Add spilOverJtag for Virtex6
 2024-02-28 22:03:53 +01:00
ZhiYuanNJ 4af0bf6ed5 update CH347 (#424) 2024-02-28 20:44:49 +01:00
Uwe Bonnes a926ab9b88 Add (Cern) VMM3 board 2024-02-28 11:50:10 +01:00
Uwe Bonnes 0e99360d1c Add (Cern) VEC_V6 Board 2024-02-28 11:50:10 +01:00
Uwe Bonnes 354d3f86ab Virtex6: Add spiOverJtag for Virtex6, detect xc6vlx130 and provide bitfile for xc6vlx130tff784 2024-02-28 11:50:10 +01:00
Uwe Bonnes 956d9355a6 Add S25FL128L flash 2024-02-28 11:50:10 +01:00
Gwenhael Goavec-Merou 85d9ca5d20 board: added digilent cmoda7_15t 2024-02-26 21:18:33 +01:00
Gwenhael Goavec 0182d592be dfu,ftdipp_mpsse: sprintf -> snprintf 2024-02-20 20:59:13 +01:00
Gwenhael Goavec-Merou 3165552994 DFU: fix code to accept tinyDFU implementation (where not altsettings have an DFU descriptor) 2024-02-15 06:45:13 +01:00
Giovanni Bruni ffc519c0e2 lattice: improve info about "BSE Error Code" from Device Status Register 2024-02-13 09:32:30 +01:00
Giovanni Bruni e923ef4059 lattice nexus boards: change from CABLE_DEFAULT (i.e. 6MHz) to CABLE_MHZ(1) (i.e. 1MHz) 
as at 6MHz the download of bitstreams is not stable.

With "not stable" we mean that:
- when dealing with Certus/Crosslink, most of the times it works
- when dealing with CertusPro devices, most of the times it doesn't work

We think this is due to the size of the bitstream and the way that the
transmission/storing is handled on the receiving side (i.e. the FPGA).
 2024-02-13 09:24:47 +01:00
Giovanni Bruni 0f9422f09a latticeBitParser: add support for loading Lattice (Nexus) encrypted bitstreams, 
by adding key and preamble of encrypted bitstreams to if statements.
 2024-02-13 09:22:34 +01:00
Michael Davidsaver daa1e38799 xvc client: handle failed ll_write() 
Avoids "Send instruction failed" in a tight loop...
 2024-02-11 14:25:00 -08:00
Michael Davidsaver 4c737b2b96 xvc client ensure send() entire buffer 2024-02-11 14:25:00 -08:00
Gwenhael Goavec-Merou 39be00fd56 Merge pull request #427 from jgroman/master 
Fix Tang Primer 25K SRAM loading when flash is erased
 2024-02-02 13:09:45 +01:00
jgroman eba9c37027 Fix SRAM loading on invalid flash 2024-02-02 12:54:17 +01:00
sigmaeo fc58ffed38 Update spiFlashdb.hpp for Macronix MX25L3233F used on Cmod A7-35T 
Digilent changed from Micron N25Q032A to Macronix MX25L3233F in 2020/2021, so this flash is needed in openfpgaloader to load to Cmod A7-35T
 2024-02-01 19:48:21 +01:00
Gwenhael Goavec-Merou f9c1aa4eed Merge pull request #423 from jgroman/master 
Add faulty MPSEE cmd 8E workaround
 2024-01-29 07:17:50 +01:00
jgroman 33eaf58869 Add faulty MPSEE cmd 8E workaround 2024-01-27 13:02:46 +01:00
Michal Sieron 1aaa1b37ac board: add Antmicro LPDDR4 Tester board 
Signed-off-by: Michal Sieron <[email protected]>
 2024-01-25 12:29:12 +01:00
Michal Sieron 59f5759888 board: add Antmicro DDR5 Tester board 
Signed-off-by: Michal Sieron <[email protected]>
 2024-01-25 12:25:07 +01:00
Michal Sieron 17939d587e board: add Antmicro DDR4 Tester board 
Signed-off-by: Michal Sieron <[email protected]>
 2024-01-25 12:23:27 +01:00
Gwenhael Goavec-Merou 308e47c5c0 Merge pull request #420 from sean-anderson-seco/xilinx-ids 
xilinx: Add remaining ZynqMP IDs
 2024-01-19 07:25:54 +01:00
Sean Anderson da0f6f6f2a xilinx: Add remaining ZynqMP IDs 
The IDs were taken from UG1085 v2.2 table 1-2.
 2024-01-18 14:50:23 -05:00
Sean Anderson 9943c3072a lattice: Add all MachXO[23] part IDs 
The version field is the only difference between many parts in the
MachXO[23] family, including between different families. Add the version
field to all parts, fixing detection of some MachXO3 parts as MachXO2s.
The id codes were extracted from the BSDL files on Lattice's website.
 2024-01-18 13:48:50 -05:00
Chuang Zhu 4148be3d31 part: 0x012bc043 is for LCMXO2-4000HC 
I found this when I was trying to program a LCMXO2-4000HC, but
openFPGALoader said it is a LCMX03LF-4300C:

	$ openFPGALoader --detect
	No cable or board specified: using direct ft2232 interface
	Jtag frequency : requested 6.00MHz   -> real 6.00MHz
	index 0:
		idcode 0x12bc043
		manufacturer lattice
		family MachXO3LF
		model  LCMX03LF-4300C
		irlength 8

From what I found on the internet, the idcode for LCMX03LF-4300C seems
to be 0x612BC043:
https://bsdl.info/details.htm?sid=b483da5dec63d6cd88ca59b002289d77
 2024-01-11 10:00:02 +08:00
Gwenhael Goavec-Merou a3826614b3 gowin: writeFLASH: increase delay before CRC check (required for 9K device) 2024-01-09 19:56:53 +01:00
Gwenhael Goavec-Merou 0b59efcb42 src/gowin: GW5A/SPI flash: adding delay after erase flash and after SPI mode instruction. Seems fixed write error. 2024-01-09 18:48:21 +01:00
Gwenhael Goavec-Merou 62ad3a3003 gowin: fix flash erase for GW1NSR-4C: during shiftDR sequence TDI MUST be 0x0000 2024-01-04 07:24:02 +01:00
Gwenhael Goavec-Merou c51dbcb0ed Merge pull request #410 from pu-cc/gatemate-chain-fix 
gatemate: fix configuration byte alignment in jtag chains
 2023-12-27 14:42:29 +01:00
Patrick Urban 001f20c884 gatemate: use more suitable change to RUN_TEST_IDLE state 2023-12-27 13:38:13 +01:00
Catherine 8c6c0ee85a Add WebAssembly support. 2023-12-22 21:07:33 +00:00
Catherine bca3bd6623 Use correct format specifier for printing uint64_t. 2023-12-22 21:07:23 +00:00
Gwenhael Goavec-Merou cd40de37cb main: allows mcufw only mode for gowin 2023-12-14 13:13:48 +01:00
Gwenhael Goavec-Merou 22f33618b0 gowin: mcufw may be written without fs (but this erase all memory) 2023-12-14 13:13:29 +01:00
Gwenhael Goavec-Merou 2093ce7520 gowin: fix gw1n external flash access 2023-12-14 11:48:14 +01:00
Gwenhael Goavec-Merou 1dbc9e664b gowin: programFlash/writeFlash: disable previous rewrite (fix write with tangnano4k) 2023-12-14 11:38:34 +01:00
Patrick Urban 1dfdec6ce1 gatemate: fix configuration in jtag chains 2023-12-12 10:21:30 +01:00
Gwenhael Goavec-Merou ed547ed893 boards: adding AMD Virtex UltraScale+ FPGA VCU1525 Acceleration Development Kit 2023-12-11 12:23:37 +01:00
Gwenhael Goavec-Merou d8186c5e8a gowin: GW5AST work around 2023-12-11 07:20:37 +01:00
Gwenhael Goavec-Merou 1c7a4afd01 ftdipp_mpsse: display/typo 2023-12-11 07:18:02 +01:00
Gwenhael Goavec-Merou bd917d51ef gowin: try second eraseSRAM before writeSRAM. Not always working but better... 2023-12-10 08:14:06 +01:00
Tim Paine b70a3991cc Add pynq-z1 board 2023-12-08 14:51:38 -05:00
Gwenhael Goavec-Merou 2a2435ecbe board: Xilinx KCU105 (Kintex Ultrascale xcku040) 2023-12-08 16:00:59 +01:00
Gwenhael Goavec-Merou 807d794703 latticeBitParser: add ECP3 VERIFY ID support (avoid to fail with bitstream) 2023-12-08 07:07:35 +01:00
Gwenhael Goavec-Merou fb587e73d8 gowin: Fix clk cycle after sending a command, don't read status register programSRAM sequence 2023-12-04 07:25:43 +01:00
Gwenhael Goavec-Merou 0dcd851187 gowin: avoid multiple status register access 2023-12-04 07:05:40 +01:00
Gwenhael Goavec-Merou 01d6244a0f gowin: Fix status register parse for GW5AST 2023-12-04 07:01:56 +01:00
Gwenhael Goavec-Merou 8007ffe263 xilinx: lint more happy 2023-11-25 15:14:32 +01:00
bma 234f7f5a35 XADC and DNA for Xilinx FPGA (#407) 
* xilinx: add XADC and DNA args, see https://github.com/cfib/openFPGALoaderXADC/tree/XADC_3
parts: add xcku060
* doc: add xcku060
 2023-11-25 08:47:24 +01:00