205e6f9ea5
spiOverJtag/build.py: fixed model value for kintex7 with ISE
2025-09-25 17:09:38 +02:00
f8ae76e771
spiOverJtag/build.py: added default value for pkg variable
2025-09-25 15:47:48 +02:00
a7b72321fe
spiOverJtag: added xc7k70tfbg676 variant
2025-09-24 16:48:02 +02:00
8e6eb1085c
spiOverJtag/build.py: simplify Kintex7 uses
2025-09-24 16:46:57 +02:00
fdc9edc6cb
spiOverJtag/xilinx_spiOverJtag.v: spartan3e: spi_drck -> drck
2025-09-22 10:18:24 +02:00
29a5bc3515
spiOverJtag/xilinx_spiOverJtag.v: fixed code for virtex6 targets
2025-09-20 18:05:55 +02:00
1ccc2a0d5b
spiOverJtag/xilinx_spiOverJtag.v: can't declare spi_clk for spartan3e device. Fixed sck assign for spartan3e
2025-09-20 17:30:10 +02:00
5e67fee9f5
spiOverJtag/build.py: gzip file must be produces for all Xilinx devices
2025-09-17 20:16:03 +02:00
06b4e2f143
spiOverJtag/xilinx_spiOverJtag.v: don't redeclares tdo for spartan3e
2025-09-17 11:55:52 +02:00
b06220f71f
spiOverJtag/build.py: added default value for model variable
2025-06-30 18:26:59 +02:00
6c4a48f445
spiOverJtag: reworks Artix and Spartan 7 approach:
...
For a specific FPGA size, pins name is only a matter of package,
internally physical pads are the same: a unique bitstream per size is
necessary. This also simplify build.py by removing complexity to
extract model, size and package.
- a dict is added with supported packages per size
- only one bitstream is produces for artix/spartan7 size, package+size bitstreams are only symlinks.
- constraints files are also updated with BSCANE2/DRCK clocks constraints
- the gz is produces by build.py instead of by the Makefile
- all possibles bitstreams for XC7A/XC7S are now present.
2025-05-26 09:53:25 +02:00
589b161d4e
spiOverJtag/.gitignore: ignore vivado files
2025-05-26 09:53:20 +02:00
971a8db4e9
spiOverJtag: introduce a new spiOverJtag (v2) core able to work with complex JTAG chain
2025-05-11 09:13:25 +02:00
40a588fb2c
Add xcau15p (xcau15p_ffvb676) support ( #547 )
...
Co-authored-by: vbuitvydas <v.buitvydas@limemicro.com>
2025-05-10 07:02:21 +02:00
6e05a7fa25
Add support for Artix A7 15t
...
Tested on real hardware, connecting through Linux gpiod
2025-04-08 15:31:41 +00:00
fdf24a824e
add xc7a50tcsg325
2025-04-01 22:19:18 +03:00
2535170267
spiOverJtag: add xc7s75fgga676
2025-03-25 10:32:12 +01:00
d61e147989
added 1.35v csg325 build and Macronix flash
2025-02-15 14:24:42 -07:00
43fcc6ce2c
Add ID and spiOverJtag bitstream for Stratix V GS D5
2024-10-10 19:59:31 +02:00
f3a48fb3b1
spiOverJtag: add support and bitstreams for xcku040 and xcku060
2024-09-25 07:24:09 +02:00
81422b6ca3
Merge pull request #481 from acceleratedtech/jwise/ti180-soj
...
efinix: add spiOverJtag support for Ti180J484
2024-08-31 08:20:04 +02:00
ad01d986c1
adding support for cyc5000
2024-08-24 21:32:00 -07:00
286b34b14d
spiOverJtag: add support for Ti180J484
2024-08-19 21:29:00 -04:00
084d291073
spiOverJtag: added basic efinix build script (WIP)
2024-08-19 09:57:15 +02:00
572b0978f6
[enh] added t13f256 SPI flash support
2024-08-17 15:41:44 +02:00
7fc222d50f
spiOverJtag: added bitstream for Xilinx Spartan6 xc6slx25csg324
2024-08-03 11:01:26 +02:00
bdaba6e7da
spiOverJtag: added Xilinx Spartan6 model: 25T package: CSG324 (xc6slx25tcsg324)
2024-08-03 08:53:18 +02:00
406a6baa6f
spiOverJtag: Xilinx spartan7 xc7s6ftgb196 bitstream
2024-08-01 08:16:16 +02:00
dc43795798
spiOverJtag: Add xc7a200tfbg676 support (tested on hardware).
2024-06-18 15:44:33 +02:00
66c47fe3bd
Add support for EP4CE6E22 and EP4CE10F17
2024-04-30 14:51:29 -04:00
55b094ce00
add EP4CGX150
2024-04-27 16:18:23 +07:00
7bbaef0c87
spiOverJtag: added xc6slx45tfgg48 support
2024-03-28 22:14:27 +01:00
21c2264382
xc7vx330tffg1157: Allow to build and provide spiOverJtag_xc7vx330tffg1157.bit
2024-03-01 13:38:23 +01:00
52ade9df6e
spiOverJtag: XC6SLX...L may need other pin constraints as XC6SLX...
...
- Checked and handled for XC6Sxxx(T)fgg484
2024-02-28 12:59:22 +01:00
75e086cd55
spiOverJtag: Remove obsolete xc6 directory
2024-02-28 12:59:12 +01:00
354d3f86ab
Virtex6: Add spiOverJtag for Virtex6, detect xc6vlx130 and provide bitfile for xc6vlx130tff784
2024-02-28 11:50:10 +01:00
3ea541cd8e
xilinx_spiOverJtag.v: Rearrange for better extensibility
...
- Use `ifdef ... `elsif ... `endif for better seperation
2024-02-28 11:49:51 +01:00
0a92adf8a6
spiOverJtag: Add constr_xc7k_fbg676.xdc
2024-02-28 10:00:13 +01:00
7363708f11
spiOverJtag: Fix errors on xc6slx150tfgg484
2024-02-28 09:59:44 +01:00
829b5eb099
spiOverJtag: Add missing xc6s_tqg144 constraint
2024-02-28 09:59:16 +01:00
9e2edeb6c1
spiOverJtag: added xc7a15tcpg236 bitstream
2024-02-26 21:15:36 +01:00
d2f31860cd
spiOverJtag: add support for xc7k70tfbg484
...
Signed-off-by: Michal Sieron <msieron@antmicro.com>
2024-01-25 12:42:11 +01:00
63c1950f2f
Add xc7k70t and small fixes for xc7k160t
2023-11-09 07:45:46 +07:00
ba0a2f3e26
spiOverJtag: Add xc7a35tfgg484 bitstream.
2023-10-13 11:13:47 +02:00
9de0f30137
spiOverJtag: Add xc7a35tfgg484 support.
2023-10-13 11:13:29 +02:00
ddac3df394
spiOverJtag: Add xcku3p-ffva676 bitstream.
2023-10-12 18:09:41 +02:00
87a21fe74e
spiOverJtag: Add xcku3p_ffva676 support.
2023-10-12 18:02:23 +02:00
7a637a1085
spiOverJtag/xilinx_spiOverJtag: Update code since Virtex Ultrascale has apparently been replaced with Xilinx Ultrascale.
2023-10-12 18:00:59 +02:00
5ac611c124
spiOverJtag: intel/altera cyclone10 LP 10CL016YU484C8G
2023-08-05 11:48:06 +02:00
91f2900f0c
add support for colorlight-i9+ board + spiOverJtag/spiOverJtag_xc7a50tfgg484.bit.gz
2023-06-30 11:36:32 +02:00
Gwenhael Goavec-Merou
Tomserv-512
Nate White
Neo
Franck Jullien
AEW2015
Andreas Galauner
bma
Greg Steiert
Joshua Wise
Gwenhael Goavec-Merou
Charles-Henri Mousset
Florent Kermarrec
Evan Kahn
Hans Baier
Uwe Bonnes
Gwenhael Goavec-Merou
Michal Sieron
Hans Baier
Stéphane Chevigny