b76840b20d
doc/FPGAs.yml: added Kintex UltraScale+ reference
2025-11-05 18:43:38 +01:00
530b7a9993
Merge pull request #593 from AEW2015/master
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basic PDI prog for Spartan Ultrascale+
2025-10-23 06:50:14 +02:00
648a4a833a
basic PDI prog for Spartan Ultrascale+
2025-10-23 06:44:19 +02:00
03be134cdd
Merge pull request #591 from hennomann/patch-1
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Update part.hpp to support Lattice LFE3-150EA device
2025-10-02 12:02:15 +02:00
617cd29dff
Update part.hpp to support Lattice LFE3-150EA device
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This PR adds device ID support for the Lattice ECP3 LFE3-150EA.
Previously, only the LFE3-70E was supported.
We've tested the implementation and confirmed it works as expected.
We're happy to contribute to expanding ECP3 device support!
2025-10-02 11:32:19 +02:00
205e6f9ea5
spiOverJtag/build.py: fixed model value for kintex7 with ISE
2025-09-25 17:09:38 +02:00
f8ae76e771
spiOverJtag/build.py: added default value for pkg variable
2025-09-25 15:47:48 +02:00
8694b3c295
board: added HyVision PCIe OPT01 rev.F (Kintex7 xc7k70tfbg676)
2025-09-24 16:56:46 +02:00
a7b72321fe
spiOverJtag: added xc7k70tfbg676 variant
2025-09-24 16:48:02 +02:00
8e6eb1085c
spiOverJtag/build.py: simplify Kintex7 uses
2025-09-24 16:46:57 +02:00
13cf0c59b9
xilinx: load_bridge: uses configBitstreamParser getFilename to print real name instead of theorical (with or without .gz)
2025-09-24 08:07:27 +02:00
6935936a92
configBitstreamParser: added filename getter
2025-09-24 08:06:28 +02:00
39b3ca5871
spiInterface: all methods: added a \n after command displayed (avoids unclear message when calee methods uses printxxx)
2025-09-24 08:06:06 +02:00
fdc9edc6cb
spiOverJtag/xilinx_spiOverJtag.v: spartan3e: spi_drck -> drck
2025-09-22 10:18:24 +02:00
29a5bc3515
spiOverJtag/xilinx_spiOverJtag.v: fixed code for virtex6 targets
2025-09-20 18:05:55 +02:00
6df4bce1fd
xilinx: allows Flash write for Xilinx Spartan3 targets
2025-09-20 17:31:32 +02:00
1ccc2a0d5b
spiOverJtag/xilinx_spiOverJtag.v: can't declare spi_clk for spartan3e device. Fixed sck assign for spartan3e
2025-09-20 17:30:10 +02:00
5e67fee9f5
spiOverJtag/build.py: gzip file must be produces for all Xilinx devices
2025-09-17 20:16:03 +02:00
06b4e2f143
spiOverJtag/xilinx_spiOverJtag.v: don't redeclares tdo for spartan3e
2025-09-17 11:55:52 +02:00
1fc7539538
Prepare v1.0.0 release
2025-09-12 16:00:32 +02:00
e2c55f24c0
part: fixed cyclone III/IV/10 LP IDCODE (same code for all families)
2025-09-12 13:26:36 +02:00
c102426b78
Add altera EP4CE30 ( #584 )
2025-09-08 08:34:37 +02:00
2e12478a65
99-openfpgaloader.rules: added Altera usb-blasterIII rule
2025-09-03 17:34:49 +02:00
19a8df433a
.github/workflows/Test.yml: fixed CI with windows (msys2/setup-msys2 master looks broken)
2025-09-03 17:34:19 +02:00
cfddee3611
colognechip: add bulk erase + quad enable features and simplify spi_wait overload ( #582 )
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* colognechip: add bulk erase + quad enable features and simplify spi_wait overload
* colognechip: remove unnecessary code in `set_quad_bit` and `bulk_erase_flash`
2025-09-03 16:26:16 +02:00
501d37e351
Merge pull request #581 from pu-cc/at25ql321
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spiFlashdb: add AT25QL321
2025-09-03 14:38:11 +02:00
26849d089b
Merge pull request #580 from pu-cc/fix-spiflash-qen
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spiFlash: mask RDSR_WIP instead of RDSR_WEL while waiting for completion
2025-09-03 14:37:16 +02:00
41e4a93f80
spiFlashdb: add AT25QL321
2025-09-03 14:11:28 +02:00
db64ec92cb
spiFlash: mask RDSR_WIP instead of RDSR_WEL while waiting for completion
2025-09-03 13:55:31 +02:00
bdcdea9a2f
cable: added altera usb blaster III variant
2025-08-27 18:26:17 +02:00
46a0560927
display: std::endl -> \n
2025-08-26 17:51:31 +02:00
850c3d74e0
progressBar: added eol for each progressBar update when no STDOUT_FILENO
2025-08-26 17:49:01 +02:00
2580aed994
esp_usb_jtag: added support for https://github.com/espressif/esp-usb-bridge + small adjusts
2025-08-25 09:38:00 +02:00
c818641cae
main: list_boards: print 'Undefined' when fpga_part or cable_name is empty
2025-08-07 11:00:49 +02:00
bc864100ff
main: list_boards now displays fpga_part too
2025-08-07 09:53:28 +02:00
6a1e0ff65e
Merge pull request #575 from 0xDRRB/master
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Add Altera Cyclone 10 LP 10CL080 support
2025-07-29 09:58:31 +02:00
c51c53ee33
Add Altera Cyclone 10 LP 10CL080
2025-07-28 13:27:06 +02:00
a53aedb137
gowin: added (undocumented) sequence to be performed when CRC Error bit is set
2025-07-20 10:23:19 +02:00
42a4801180
cable: added Altera USB Blaster III (missing link in doc
2025-07-20 09:36:53 +02:00
388f0b4c90
spiFlashdb: added XTX XT25F32B-S chip
2025-07-20 09:32:12 +02:00
5997c202fc
99-openfpgaloader.rules: added entry for ULX3S/ULX4M (DFU mode)
2025-07-19 09:45:26 +02:00
b99672b69e
board: added ULX4M (DFU)
2025-07-19 09:45:04 +02:00
5e91e20e29
Merge pull request #571 from pu-cc/gatemate-jtag-bypass
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colognechip: Simplify handling of JTAG bypass bits
2025-07-10 09:43:50 +02:00
3b932dc542
colognechip: Simplify number of jtag bypass bits
2025-07-09 16:13:18 +02:00
3b1a40b798
part.hpp: MAX10: only keep size+Single(S)/Dual-supply(D). Sort between single-supply and dual-supply
2025-07-04 07:28:05 +02:00
880ed6f5c9
Merge pull request #568 from csantosb/master
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Document use of udev rules under GuixSystem
2025-07-03 10:52:03 +02:00
626084947d
doc/guide/install.rst: udev rules instructions under GuixSystem.
2025-07-03 10:43:40 +02:00
4bd9840e46
altera: fix Wc99-designator
2025-07-02 07:17:17 +02:00
b06220f71f
spiOverJtag/build.py: added default value for model variable
2025-06-30 18:26:59 +02:00
b2aa12b582
spiFlash, spiFlashdb: added global_lock flag and uses it instead of jedec_id ( #566 )
2025-06-30 18:26:22 +02:00
Gwenhael Goavec-Merou
Andrew E Wilson
hennomann
Andy
Patrick Urban
Denis Bodor
Cayetano Santos