spiOverJtag: added basic efinix build script (WIP)
This commit is contained in:
Gwenhael Goavec-Merou
parent
d6b58cdb71
commit
084d291073
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@ -24,10 +24,18 @@ ALTERA_PARTS := 10cl025256 10cl016484 10cl055484 \
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ep4ce622 ep4ce1017 ep4ce2217 ep4ce1523 ep4ce11523 ep4cgx15027 5ce223 5ce423 5ce523 5ce927
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ALTERA_BIT_FILES := $(addsuffix .rbf.gz, $(addprefix spiOverJtag_, $(ALTERA_PARTS)))
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BIT_FILES := $(ALTERA_BIT_FILES) $(XILINX_BIT_FILES)
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EFINIX_PARTS := t8f81 t13f256
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EFINIX_BIT_FILES := $(addsuffix .bit.gz, $(addprefix spiOverJtag_efinix_, $(EFINIX_PARTS)))
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BIT_FILES := $(ALTERA_BIT_FILES) $(EFINIX_BIT_FILES) $(XILINX_BIT_FILES)
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all: $(BIT_FILES)
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$(EFINIX_BIT_FILES) : spiOverJtag_efinix_%.bit.gz : tmp_efinix_%/efinix_spiOverJtag.bit
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gzip -9 -c $< > $@
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tmp_efinix_%/efinix_spiOverJtag.bit : efinix_spiOverJtag.v
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./efinix_build.py --device $*
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$(XILINX_BIT_FILES) : spiOverJtag_%.bit.gz : tmp_%/spiOverJtag.bit
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gzip -9 -c $< > $@
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tmp_%/spiOverJtag.bit : xilinx_spiOverJtag.v
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@ -0,0 +1,175 @@
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#!/usr/bin/env python3
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import argparse
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import datetime
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import os
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import pathlib
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import pprint
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import re
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import sys
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from edalize.edatool import get_edatool
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from edalize.flows.efinity import Efinity
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#from xml.dom import expatbuilder
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#import xml.etree.ElementTree as et
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#efinity_home = os.environ["EFINITY_HOME"]
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#script_path = efinity_home + "/scripts"
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curr_path = os.getcwd()
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efinix_pinout = {
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"Trion": {
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"F49": { # t4/t8
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"ss_n": "G3", "cclk": "F3", "cdi0": "F2", "cdi1": "F1", "cdi2": "E2", "cdi3": "D2",
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},
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"F81": { # t4/t8
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"ss_n": "J4", "cclk": "H4", "cdi0": "F4", "cdi1": "H3", "cdi2": "J2", "cdi3": "F3",
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},
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"F169": { # t13/t20
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"ss_n": "L1", "cclk": "K1", "cdi0": "J1", "cdi1": "J2", "cdi2": "F1", "cdi3": "G2",
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},
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"F256": { # t13/t20
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"ss_n": "P3", "cclk": "H3", "cdi0": "L3", "cdi1": "N1", "cdi2": "K4", "cdi3": "L2",
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},
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"F324": { # t20/t85/t120
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"ss_n": "P15", "cclk": "N13", "cdi0": "M13", "cdi1": "N14", "cdi2": "K14", "cdi3": "K18",
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},
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"F400": { # t20/
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"ss_n": "W18", "cclk": "W19", "cdi0": "Y17", "cdi1": "Y18", "cdi2": "P15", "cdi3": "R17",
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},
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"Q100": { # t13/t20
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"ss_n": "24", "cclk": "26", "cdi0": "19", "cdi1": "18", "cdi2": "8", "cdi3": "14",
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},
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"Q144": { # t20/
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"ss_n": "31", "cclk": "30", "cdi0": "29", "cdi1": "28", "cdi2": "20", "cdi3": "19",
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},
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"W80": { # t20/
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"ss_n": "K3", "cclk": "K2", "cdi0": "J1", "cdi1": "J2", "cdi2": "F1", "cdi3": "G2",
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},
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},
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}
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def gen_isf_constr(gateware_name, build_path, device_name, family, pkg):
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# Basic settings
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isf_array = [
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"# Device setting",
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"design.set_device_property(\"1A\",\"VOLTAGE\",\"3.3\",\"IOBANK\")",
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"design.set_device_property(\"1B\",\"VOLTAGE\",\"3.3\",\"IOBANK\")",
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"design.set_device_property(\"1C\",\"VOLTAGE\",\"1.1\",\"IOBANK\")",
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"design.set_device_property(\"2A\",\"VOLTAGE\",\"3.3\",\"IOBANK\")",
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"design.set_device_property(\"2B\",\"VOLTAGE\",\"3.3\",\"IOBANK\")",
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"",
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]
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# JTAG settings
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isf_array.append("# ---------- JTAG 1 ---------")
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isf_array.append("design.create_block(\"jtag_soc\", block_type=\"JTAG\")")
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isf_array.append("design.assign_resource(\"jtag_soc\", \"JTAG_USER1\", \"JTAG\")")
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jtag_pads = [
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"CAPTURE", "DRCK", "RESET", "RUNTEST", "SEL", "SHIFT", "TCK", "TDI", "TMS", "UPDATE", "TDO"
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]
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for pad in jtag_pads:
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isf_array.append(f"design.set_property(\"jtag_soc\", \"{pad}\", \"jtag_1_{pad}\", \"JTAG\")")
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# SPI pins settings
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pins = efinix_pinout.get(family).get(pkg, None)
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assert pins is not None
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pin_lst = [
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{"name" : "csn", "dir": "out", "pin": pins["ss_n"], "io_std": "3.3 V LVTTL / LVCMOS"},
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{"name" : "sck", "dir": "out", "pin": pins["cclk"], "io_std": "3.3 V LVTTL / LVCMOS"},
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{"name" : "sdi_dq0", "dir": "out", "pin": pins["cdi0"], "io_std": "3.3 V LVTTL / LVCMOS"},
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{"name" : "sdo_dq1", "dir": "in", "pin": pins["cdi1"], "io_std": "3.3 V LVTTL / LVCMOS"},
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]
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for pin_cfg in pin_lst:
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name = pin_cfg["name"]
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pin_loc = pin_cfg["pin"]
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if pin_cfg["dir"] == "in":
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isf_array.append(f"design.create_input_gpio(\"{name}\")")
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else:
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isf_array.append(f"design.create_output_gpio(\"{name}\")")
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isf_array.append(f"design.assign_pkg_pin(\"{name}\", \"{pin_loc}\")")
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isf_array.append("")
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# Save ISF file
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with open(os.path.join(build_dir, build_name+".isf"), "w") as fd:
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fd.write("\n".join(isf_array))
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if __name__ == "__main__":
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parser = argparse.ArgumentParser("SpiOverJtag for Efinix devices")
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parser.add_argument("--device", help="Efinix Device")
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args = parser.parse_args()
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assert args.device is not None
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device = args.device.upper()
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build_name = "efinix_spiOverJtag"
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build_dir = os.path.join(curr_path, f"tmp_efinix_{device.lower()}")
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timing_model = "C2" # FIXME: always usable (trion / titanium) ?
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sources = [
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{
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'name': os.path.join(curr_path, "efinix_spiOverJtag.v"),
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"file_type": "verilogSource",
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},
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{
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'name': os.path.join(build_dir, "efinix_spiOverJtag.isf"),
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"file_type": "ISF",
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},
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]
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force_restart = False
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t = re.compile(r"(T[I]*)(\d+)(\w\d+)")
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tt = t.match(device)
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if tt is None:
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print("fails")
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else:
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(fam, size, package) = tt.groups()
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assert fam in ["TI", "T"]
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family = {True:"Titanium", False:"Trion"}[fam == "TI"]
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if fam == "TI":
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device = device.replace("TI", "Ti")
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if os.path.exists(build_dir) and force_restart:
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os.rmdir(build_dir)
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if not os.path.exists(build_dir):
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try:
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os.mkdir(build_dir)
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except FileExistsError:
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pass
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gen_isf_constr(
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gateware_name = build_name,
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build_path = build_dir,
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device_name = device,
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family = family,
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pkg = package
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)
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tool_options = {
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'part' : device,
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'family' : family,
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'timing' : timing_model,
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}
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edam = {
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'name' : build_name,
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'files' : sources,
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'flow_options' : tool_options,
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'toplevel' : 'spiOverJtag',
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}
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backend = Efinity(edam=edam, work_root=build_dir)
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backend.configure()
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backend.build()
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import shutil
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shutil.copy(os.path.join(build_dir, "outflow", "efinix_spiOverJtag.bit"), build_dir)
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