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5,062 Commits 36 Branches 9 Tags 30 MiB
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5062 Commits

Author SHA1 Message Date
Miodrag Milanovic c031cbb59b cleanup 2026-02-11 11:04:11 +01:00
Miodrag Milanovic 4f468746dc clangformat 2026-02-11 10:58:57 +01:00
Miodrag Milanovic a9cc738a89 chipdb version bump 2026-02-11 10:56:47 +01:00
Miodrag Milanovic 6ebdf991af Revert "verify inversion before/after assigning bridges" 
This reverts commit 8613ee17c8.
 2026-02-11 10:56:17 +01:00
Miodrag Milanovic b537372c7d Revert "we care only if there is net" 
This reverts commit 3da2769e31.
 2026-02-11 10:56:00 +01:00
Miodrag Milanovic 3da2769e31 we care only if there is net 2026-02-11 08:45:26 +01:00
Lofty 8613ee17c8 verify inversion before/after assigning bridges 2026-02-10 14:08:59 +00:00
Miodrag Milanovic 186c910d06 handle inversion bits for pass signals 2026-02-10 11:55:42 +01:00
Miodrag Milanovic fe4584d55e allow only some pass trough for clock router 2026-02-06 11:45:47 +01:00
Miodrag Milanovic 5fc81d6d8d Fix routing conflicts issues 2026-02-06 09:58:49 +01:00
Lofty a72a593740 comment out spammy debug message 2026-02-04 17:04:58 +00:00
Lofty 0a763dd799 resource bugfix 2026-02-03 13:54:00 +00:00
Miodrag Milanovic 430325f7db Added no-cpe-cp option 2026-02-02 15:01:37 +01:00
Lofty abbf9cb017 perform per-wire resource congestion costing 2026-02-02 13:32:06 +00:00
Miodrag Milanovic cc2dfa8749 Add option to skip bridges 2026-01-27 13:27:15 +01:00
Lofty 2472b0d38e current progress 2026-01-27 11:10:09 +00:00
Lofty 86d0858308 arch API for resources 2026-01-26 09:15:19 +00:00
Miodrag Milanovic 9f9acaeb87 It is required to set all mandatory properties now 2026-01-23 10:26:52 +01:00
Miodrag Milanovic 275ba0ad81 fix formatting 2026-01-22 12:26:10 +01:00
Miodrag Milanovic 27a49487b6 Handle block and resources 2026-01-22 12:25:28 +01:00
Lofty aef841793c adapt reassign_cplines for internal resource pips 2026-01-21 15:50:36 +00:00
Miodrag Milanovic 574ede7181 produce valid netlist with propagation netlist at least 2026-01-21 09:03:53 +01:00
Lofty 5f1370cf37 mask field to resource field 2026-01-20 08:33:43 +00:00
Miodrag Milanovic 0e8a51f211 Use resources info 2026-01-19 15:10:58 +01:00
Miodrag Milanovic c163ae72a6 Add options to disable some pips 2026-01-14 12:40:57 +01:00
Miodrag Milanovic 5e611fe9be Fix ODDR 2026-01-14 09:18:31 +01:00
Miodrag Milanovic 06090528a3 remove empty if 2026-01-14 08:41:27 +01:00
Lofty e996bfab5e fix multiplier output register packing 2026-01-11 21:25:07 +00:00
Lofty c03dfdc7dc mux bridges need cell bel pins too 2026-01-11 20:01:04 +00:00
Miodrag Milanovic 3227e4d717 add ports to cell 2026-01-11 20:01:04 +00:00
Lofty d246fadd8d rough code to break cplines into subnets 2026-01-11 20:01:04 +00:00
Miodrag Milanovic fa5389d43e Fix pip masking 2026-01-11 20:01:04 +00:00
Miodrag Milanovic b3c8829fe1 create CPE_CPLINES cells and set properties on them 2026-01-11 20:01:04 +00:00
Miodrag Milanovic 944b8cfe92 Cleanup 2026-01-11 20:01:04 +00:00
Miodrag Milanovic 0b3bea6e7a handle pip masks 2026-01-11 20:01:04 +00:00
Miodrag Milanovic 3da663bf9d wip 2026-01-11 20:01:04 +00:00
Miodrag Milanovic af70c0533d remove not used variable 2026-01-11 20:01:04 +00:00
Miodrag Milanovic 9acc794661 Test passtrough concept 2026-01-11 20:01:04 +00:00
Miodrag Milanovic 4674a97664 Fix DDR nets 2026-01-11 20:01:04 +00:00
Miodrag Milanovic 88c33cca37 Fix clock router and timings 2026-01-11 20:01:04 +00:00
Miodrag Milanovic 6d5b27dc40 use additional pins 2026-01-11 20:01:04 +00:00
Miodrag Milanovic 77b498b2e3 gatemate: add alternate clock routes 2026-01-11 20:01:04 +00:00
YRabbit 1ce187ab5a
Gowin. BUGFIX. BSRAM SP separation. (#1622) 
* Gowin. BUGFIX. BSRAM SP separation.

The new SP cell must inherit the byte size - 8 or 9 bits.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Gowin. Byte Enables processing in SP.

Single Port with a data width of 32/36 is internally configured as Dual
Port with 16/18. Even and odd words are processed separately by ports A
and B.

With the advent of byte enable support, it became necessary to switch
these signals differently.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

---------

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2026-01-05 11:27:43 +01:00
Miodrag Milanović 7bd1336f88
gatemate: RAMIO packing optimization (#1602) 
* gatemate: RAMIO packing optimization

* Disable packing DFF in RAMIO
 2025-12-23 09:03:06 +01:00
Robert Ward 8ce87ab7f9
Update README to add section for mistral (cyclonev) backend (#1606) 2025-12-22 16:36:38 +01:00
Miodrag Milanović c30f810ee0
gatemate: Add LUT permutation support (#1619) 
Adds LUT permutation support
 2025-12-22 15:10:53 +01:00
Miodrag Milanović 210e6c8158
gatemate: add missing MULT timing path (#1618) 2025-12-17 11:53:10 +01:00
Miodrag Milanović f5374d6de4
himbaechel: fix parsing vopt memory issue (#1614) 2025-12-12 14:11:34 +01:00
Lofty 12342a60e6
gatemate: fix output register packing (#1608) 2025-12-12 08:52:26 +01:00
TG c46f2bbd86 ice40: Explicitly connect CIN when legalizing carry chain 
This connection is implicit as it is hardwired in the hardware.
This commit makes the connection explicit and thus appearing in the
generated netlist allowing post-rout simulation.
 2025-12-02 15:03:23 +01:00