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handle inversion bits for pass signals

This commit is contained in:
Miodrag Milanovic 2026-02-10 11:55:42 +01:00
parent fe4584d55e
commit 186c910d06
3 changed files with 18 additions and 12 deletions
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10
himbaechel/uarch/gatemate/bitstream.cc
View File

@ -65,10 +65,12 @@ struct BitstreamBackend
WireId cursor = dst_wire;
bool invert = false;
if (net_info->driver.cell && net_info->driver.cell->type == id_CPE_BRIDGE &&
net_info->driver.port == id_MUXOUT) {
int val = int_or_default(net_info->driver.cell->params, id_C_SN, 0) + 1;
invert ^= need_inversion(net_info->driver.cell, ctx->idf("IN%d", val));
if (net_info->driver.cell && uarch->pass_backtrace.count(net_info->driver.cell->name)) {
auto &bt = uarch->pass_backtrace[net_info->driver.cell->name];
if (bt.count(net_info->driver.port)) {
IdString src_port = bt[net_info->driver.port];
invert ^= need_inversion(net_info->driver.cell, src_port);
}
}
while (cursor != WireId() && cursor != src_wire) {
auto it = net_info->wires.find(cursor);

17
himbaechel/uarch/gatemate/gatemate.cc
View File

@ -472,6 +472,7 @@ void GateMateImpl::reassign_bridges(NetInfo *ni, const dict<WireId, PipMap> &net
cell->connectPort(in_port, ni);
cell->connectPort(id_MUXOUT, new_net);
pass_backtrace[cell->name][id_MUXOUT] = in_port;
num++;
@ -480,7 +481,7 @@ void GateMateImpl::reassign_bridges(NetInfo *ni, const dict<WireId, PipMap> &net
}
void GateMateImpl::reassign_cplines(NetInfo *ni, const dict<WireId, PipMap> &net_wires, WireId wire,
dict<WireId, IdString> &wire_to_net, int &num)
dict<WireId, IdString> &wire_to_net, int &num, IdString in_port)
{
wire_to_net.insert({wire, ni->name});
@ -501,7 +502,7 @@ void GateMateImpl::reassign_cplines(NetInfo *ni, const dict<WireId, PipMap> &net
const auto &extra_data = *pip_extra_data(pip);
// If not a CP line pip, just recurse.
if (extra_data.type != PipExtra::PIP_EXTRA_MUX || extra_data.resource == 0) {
reassign_cplines(ni, net_wires, dst, wire_to_net, num);
reassign_cplines(ni, net_wires, dst, wire_to_net, num, in_port);
continue;
}
@ -557,9 +558,10 @@ void GateMateImpl::reassign_cplines(NetInfo *ni, const dict<WireId, PipMap> &net
auto input_port_name = input_port_map.find(ctx->getWireName(ctx->getPipSrcWire(pip))[1]);
if (input_port_name != input_port_map.end()) {
if (cell->getPort(input_port_name->second) == nullptr)
if (cell->getPort(input_port_name->second) == nullptr) {
cell->connectPort(input_port_name->second, ni);
else
in_port = input_port_name->second;
} else
NPNR_ASSERT(cell->getPort(input_port_name->second) == ni);
}
@ -575,13 +577,14 @@ void GateMateImpl::reassign_cplines(NetInfo *ni, const dict<WireId, PipMap> &net
cell->addOutput(output_port_name->second);
cell->connectPort(output_port_name->second, new_net);
pass_backtrace[cell->name][output_port_name->second] = in_port;
num++;
reassign_cplines(new_net, net_wires, dst, wire_to_net, num);
reassign_cplines(new_net, net_wires, dst, wire_to_net, num, in_port);
} else {
// this is an internal resource pip; recurse anyway.
reassign_cplines(ni, net_wires, dst, wire_to_net, num);
reassign_cplines(ni, net_wires, dst, wire_to_net, num, in_port);
}
}
}
@ -676,7 +679,7 @@ void GateMateImpl::postRoute()
}
// traverse the routing tree to assign bridge nets to wires.
reassign_cplines(ni, net_wires, ctx->getNetinfoSourceWire(ni), wire_to_net, num);
reassign_cplines(ni, net_wires, ctx->getNetinfoSourceWire(ni), wire_to_net, num, IdString());
for (auto &pair : net_wires)
ctx->unbindWire(pair.first);

3
himbaechel/uarch/gatemate/gatemate.h
View File

@ -114,6 +114,7 @@ struct GateMateImpl : HimbaechelAPI
MultiDieStrategy strategy;
dict<int, IdString> index_to_die;
dict<IdString, int> die_to_index;
dict<IdString,dict<IdString, IdString>> pass_backtrace;
private:
bool getChildPlacement(const BaseClusterInfo *cluster, Loc root_loc,
@ -129,7 +130,7 @@ struct GateMateImpl : HimbaechelAPI
void reassign_bridges(NetInfo *net, const dict<WireId, PipMap> &net_wires, WireId wire,
dict<WireId, IdString> &wire_to_net, int &num);
void reassign_cplines(NetInfo *net, const dict<WireId, PipMap> &net_wires, WireId wire,
dict<WireId, IdString> &wire_to_net, int &num);
dict<WireId, IdString> &wire_to_net, int &num, IdString in_port);
void repack();
bool get_delay_from_tmg_db(IdString id, DelayQuad &delay) const;