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10 Commits

Author SHA1 Message Date
Miodrag Milanović 0399b8865e
gatemate: Enable placing RAM halfs (#1544) 
* gatemate: Split BRAMs into halfs

* Cleanups

* move code arround

* optmize remapping halfs

* Name RAM cells

* fix cluster setting for cascade mode

* attach ECC pins

* rewire global clocks

* bump chip database version

* Fix KEEPER setting

* Fix conflict check

* cleanup
 2025-09-02 08:03:22 +02:00
Miodrag Milanovic e1ba78094f gatemate: clean data bitmask 2025-08-27 12:28:58 +02:00
Miodrag Milanovic 2b203d21ae gatemate: add missing RAM port mapping 2025-08-27 10:37:10 +02:00
Miodrag Milanovic 84234e7d79 gatemate: delay, assign proper RAM clock 2025-08-25 10:55:19 +02:00
Miodrag Milanović 2d7d1e2408
gatemate: optimizations and cleanups (#1517) 
* Add log output

* Optimize CC_LUT1

* Update tests

* Optimize CC_LUT2 as well

* Use init enumerations

* Merge DFF in MX4

* Move repack code

* Move ramio code to pack_cpe

* Merge LUT1/2 to ADDF inputs

* Note actual CPE ports

* Merge DFF in ADDF

* Update FF params and ports first

* Check if DFFs are compatible before merging

* Optimize DFF/Latch

* Add reporting of optimized cells

* Optimize MX2/4

* Add statistics

* Use special nets for VCC/GND to skip using name

* Add warning for carry chain split

* Merge FFs where possible

* Cleanup

* Keep statistics out for now

* Add logs for packing sections

* review fixes

---------

Co-authored-by: Lofty <dan.ravensloft@gmail.com>
 2025-07-17 08:50:24 +02:00
Miodrag Milanovic bac5a9145f gatemate: memory clock signal handling 2025-05-29 13:26:35 +02:00
Miodrag Milanovic 9994fdb393 gatemate: make sure to use latest chipdb 2025-05-27 15:37:25 +02:00
Miodrag Milanović 12f597dcd1
gatemate: propagate clock constraints on input ports (#1497) 2025-05-26 11:16:45 +02:00
Miodrag Milanović 6c3956c3b9
gatemate: BRAM cascade mode support (#1487) 
* BRAM cascade mode support

* Removed unused connections

* Exclusive connection
 2025-05-19 09:55:11 +02:00
Miodrag Milanović 764b5402e8
gatemate: Initial SERDES support (#1476) 
* Initial SERDES support

* use static array for default values

* Split pack into multiple files

* Pre-place BUFG and related cells
 2025-05-06 15:56:26 +02:00