* Gowin. DSP. Implement MULT12x12.
The 5A series DSP differs from previous ones. Many things have been
greatly simplified: there are only two control signals of one type per
cell (2 CLK, 2 CE and 2 RESET), and these signals are now explicitly
specified in the DSP attributes, which makes the automatic assignment
mechanism unnecessary for them.
The DSP occupies 3 cells instead of nine due to the exclusion of 4
low-bit multipliers - now there are only two 12x12. There will naturally
be clusters, but they will be simpler and consist of other primitives.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Implement MULTADDALU12X12.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
chore: seems like working pcf
feat: add reg support and clean up
chore: add clean up
delay io check and add cell timing min-max delay
fix rebase error
better pcf syntax
add regex support for prohibit command
fix regex and repeat create
fix cell can potentially have no bel
fix IO
chore: clean up
chore: review comment
feat: set pseudo cell loc by wire info
yosys based IO insert
finalise
final finalise
* gowin: Update arch gen to use msgspec chipdb format
Apycula now uses msgspec MessagePack serialization instead of pickle
for the chipdb files. This change:
- Replaces pickle with msgspec via load_chipdb()
- Changes file extension from .pickle to .msgpack.gz
- Updates grid access patterns for new Device structure where
db.grid[y][x] returns ttyp (int) directly, use db[y, x] for Tile
Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
* Update chipdb extension to .msgpack.xz
Apicula switched from gzip to lzma compression for chipdb files.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
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Co-authored-by: Claude Opus 4.5 <noreply@anthropic.com>
Only one bit per macro is responsible for the bit width of operands. We
add operand width tracking and do not allow different operands to be
combined in a single macro.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Add GW5AST-138C chip.
The ability to perform P&R for the largest GW5A series chip currently
available has been added, which has its own characteristics:
- the need to invert pin function configuration signals - these
signals are not part of the design, but are nextpnr command line
keys for specifying the activation of alternative pin functions such as
I2C;
- some clock PIPs are encoded not by fuses, but by applying VCC/GND to
special inputs. This is also not part of the design and is not a
dynamic clock selection primitive - it is simply an addition to the
fuses.
- added check for DFF and SSRAM placement in upper slots - prior to
this chip, SSRAM was not supported and there was no need for this
check.
- since the chip is divided into two parts in terms of the global
clock network, a flag is introduced to indicate which part the wire
belongs to. This is only requested for clock wires.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Fix style.
Use C++ type cast.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. BUGFIX. BSRAM SP separation.
The new SP cell must inherit the byte size - 8 or 9 bits.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* Gowin. Byte Enables processing in SP.
Single Port with a data width of 32/36 is internally configured as Dual
Port with 16/18. Even and odd words are processed separately by ports A
and B.
With the advent of byte enable support, it became necessary to switch
these signals differently.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
This connection is implicit as it is hardwired in the hardware.
This commit makes the connection explicit and thus appearing in the
generated netlist allowing post-rout simulation.
The TLVDS_IBUF_ADC IO primitives have been implemented, which provide a
signal for ADC bus 2. These differential IO primitives also have an
additional input that allows them to be disabled, thereby providing
dynamic switching of the signal source for the ADC.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
ADC support for GW5A-25 chips has been added.
The inputs of this primitive are fixed and do not require routing,
although they can be switched dynamically.
The .CST file also specifies the pins used as signal sources for the
bus0 and bus1 ADC buses.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gatemate: handle default parameters for IO
This is probably a VHDL specific issue. In VHDL, there is no
black-box. Primitive instantiations are done using VHDL component
instantiations and the component must have been declared with all its
ports and parameters (generic). Currently the components are
translated from cells_sim.v and cells_bb.v
If a user doesn't override a parameter, the default value is used
instead. As a consequence, nextpnr can have 'UNDEFINED' for DRIVER
or SLEW parameters of CC_IOBUF. I think this is a main difference
with verilog, where unspecified parameters do not appear.
With this change, the UNPLACED value of PIN_NAME and UNDEFINED value
of DRIVE are simply ignored.
* gatemate/pack_io.cc: also handle UNDEFINED for id_SLEW
Since ctx->getArchArgs() no longer returns architecture-specific
arguments, we read the args field directly.
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
* gatemate: Use GATEMATE_DIE attribute to select placement die
* add DIE parameter in CCF
* add penalty delay when crossing between dies
* Add predictDelay
myrtle
YRabbit
Kelvin Chung
Pepijn de Vos
bwisn
Miodrag Milanovic
Patrick Urban
Darren Kulp
Robert Ward
Lofty
TG
tgingold