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5009 Commits

Author SHA1 Message Date
Lofty a48acec92e route clocks from source to sink 2025-09-16 11:00:44 +01:00
Lofty efff6f90f3 Revert "Do not use actual pip delay, determine best by number of passed pips" 
This reverts commit c66e422dd0.

We want to guarantee minimum clock skew, so we need pip delay.
 2025-09-16 09:45:08 +01:00
Lofty 80255e3611 log number of clock net users 2025-09-16 09:34:50 +01:00
Lofty 5ce34b5964 another multiplier fix 2025-09-16 08:38:05 +01:00
Lofty 395554aefe another multiplier fix 2025-09-16 08:29:45 +01:00
Lofty a3f94eaf2a another multiplier fix 2025-09-16 08:13:32 +01:00
Lofty 731f906f9a another multiplier fix 2025-09-16 08:00:07 +01:00
Lofty e3fa85b8b2 another multiplier fix 2025-09-15 17:42:10 +01:00
Lofty c347941727 another multiplier fix 2025-09-15 16:01:27 +01:00
Lofty ea85132f17 another multiplier fix 2025-09-15 15:48:12 +01:00
Lofty 2452061824 another multiplier fix 2025-09-15 12:08:00 +01:00
Lofty bd6e9cd3c1 another multiplier fix 2025-09-15 11:05:26 +01:00
Lofty b119041585 another multiplier fix 2025-09-15 10:43:19 +01:00
Lofty 20cf497e15 another multiplier fix 2025-09-15 10:37:05 +01:00
Lofty 50a18611ef another multiplier fix 2025-09-15 10:32:37 +01:00
Lofty 500840ae6b another multiplier fix 2025-09-15 10:18:30 +01:00
Lofty 50299469fc another multiplier fix 2025-09-15 09:48:22 +01:00
Lofty e2d882b056 another multiplier fix 2025-09-15 09:31:36 +01:00
Lofty 9a1c25d83b another multiplier fix 2025-09-15 09:21:19 +01:00
Lofty 59285f3332 another multiplier fix 2025-09-15 09:13:04 +01:00
Lofty 2583f01e29 another multiplier fix 2025-09-15 09:05:52 +01:00
Lofty 14030606a8 another multiplier fix 2025-09-15 09:00:17 +01:00
Lofty bc52b33f94 another multiplier fix 2025-09-15 08:46:25 +01:00
Lofty b4ef4cace9 another mult fix 2025-09-12 17:26:20 +01:00
Lofty 1ba1829a8f more multiplier fixes 2025-09-12 16:47:45 +01:00
Miodrag Milanovic 0412ef7144 proper parameter check 2025-09-12 15:30:26 +02:00
Miodrag Milanovic 485def603a optimize 2025-09-12 14:14:57 +02:00
Miodrag Milanovic c66e422dd0 Do not use actual pip delay, determine best by number of passed pips 2025-09-12 13:39:37 +02:00
Miodrag Milanovic 48cb371d27 fix clock routing 2025-09-12 10:54:46 +02:00
Miodrag Milanovic 2823ea385a add PLL delays 2025-09-12 10:52:54 +02:00
Miodrag Milanovic f24630c02b tried fixing clock router 2025-09-11 18:48:50 +02:00
Miodrag Milanovic 10765f7516 cleanup 2025-09-11 16:54:21 +02:00
Miodrag Milanovic 65d47d0183 add pip delays 2025-09-11 16:54:21 +02:00
Miodrag Milanovic 30ebf540c3 do not need node delay 2025-09-11 16:54:21 +02:00
Lofty ce0a37f666 a few multiplier router fixes 2025-09-11 15:54:02 +01:00
Miodrag Milanovic 72960a052e add plane info for node pips 2025-09-11 11:07:48 +02:00
Miodrag Milanovic f669ed54e6 convert nodes to pips 2025-09-11 10:35:13 +02:00
Miodrag Milanovic b8d2372019 gatemate: BUFG must be optional 2025-09-10 14:42:47 +02:00
Miodrag Milanović 8ac7ed161a
gatemate: code cleanup and netlist fix (#1554) 2025-09-10 14:04:42 +02:00
myrtle 9715a1d565
heap: Allow chains to ripup other chains (opt-in only) (#1552) 
Signed-off-by: gatecat <gatecat@ds0.me>
 2025-09-05 09:02:19 +02:00
Miodrag Milanović 141abe60a6
gatemate: cleanup BRAM handling (#1551) 2025-09-05 08:37:29 +02:00
Miodrag Milanović 21bfda4165
gatemate: fix fourgroup for multi die (#1550) 2025-09-03 12:20:11 +02:00
Lofty f238e2c4a5
okami: remove (#1549) 2025-09-02 19:42:07 +02:00
Miodrag Milanović 3eb682bcbb
gatemate: use CPE bridge (#1538) 
* Add bridge support

* Use bridge only if CPE is unused

* do not use CPE_MULT for MUX routing

* Fixed and documented

* delay for CPE_BRIDGE

* Convert bridge pips into bels

Co-authored-by: Miodrag Milanovic <mmicko@gmail.com>

* recursively reassign bridges

* reconnect cell ports to new nets

* handle inversion bits

* sort data in output for easier compare

* one to be removed after testing

* debug message

* Remove need for notifyPipChange

* use same logic for detecting bridge pips

* make sure that the pip used is the one assigned

* one wire may feed multiple ports

* remove #if

* clean up wire binding

* add debugging

* fix

* clangformat

* put back to error

* use tile instead of getting name out of bel/pip

* bump chipdb

* adressing review comments

* Addressed last one

---------

Co-authored-by: Lofty <dan.ravensloft@gmail.com>
 2025-09-02 18:00:01 +02:00
Miodrag Milanović 4e4f4ab113
gatemate: update bounding box (#1548) 2025-09-02 14:04:28 +02:00
Miodrag Milanović 0399b8865e
gatemate: Enable placing RAM halfs (#1544) 
* gatemate: Split BRAMs into halfs

* Cleanups

* move code arround

* optmize remapping halfs

* Name RAM cells

* fix cluster setting for cascade mode

* attach ECC pins

* rewire global clocks

* bump chip database version

* Fix KEEPER setting

* Fix conflict check

* cleanup
 2025-09-02 08:03:22 +02:00
YRabbit a18bd2e055
Gowin. BUGFIX. Add data about gate wires. (#1547) 
Very rarely (about once a year), the dedicated clock router would
malfunction, issuing an incorrect route.

The reason turned out to be the so-called gate wires to the global clock
wire system from the logic. Among the PIPs for which these wires are
sinks, there are PIPs where the sources are also clock wires.

This leads to the possibility of feeding the clock signal back into the
gate and again into the global clock MUX.

If handled carelessly, this can lead to a complete loop.

But the loop option itself is particularly useful in the case of DCS
(dynamic clock selection) - the fact is that because these primitives
have four clock inputs and each of them could theoretically address all
56 clock sources, but in practice there are not enough wires and the DCS
inputs cannot serve as sinks for all clock sources.

The simplest solution (and the one that currently works) is to use the
gate to re-enter the clock system, but this time changing the clock
source.

This commit explicitly marks wires as gates and removes the possibility
of looping (however unlikely it may be) where a loop is not needed.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2025-09-02 07:51:08 +02:00
YRabbit 7d2caf6939 Gowin. Fix style. 
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2025-09-01 16:14:49 +01:00
YRabbit 75aa8d16ac Gowin. Implement on-chip oscillator. 
A programmable on-chip crystal oscillator has been implemented for the
GW5A series.

A critical innovation in this series was the change in the nature of the
OSC output pin—it now belongs to the clock wires, and therefore the
routes must be made with a special global router, as there is no
possibility of using routing through general-purpose PIPs.

At the same time, we are transferring the outputs of all previous
generations of OSC to potential clock wires. At the moment, this will
not affect the way they are routed - they will still end up as segments
as before, but in the future we may optimize the mechanism.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2025-09-01 16:14:49 +01:00
YRabbit bc086c012f
Gowin. Optimize ALU wiring (#1543) 
* Gowin. Optimize ALU wiring

Interestingly, although VCC and GND sources are present in each cell,
they cannot be connected directly to all LUT inputs. Instead, additional
PIPs are used.

A very simple ALU optimization: once we detect that one of the inputs is
a constant, we modify the main LUT that describes the ALU function so
that this primitive input is ignored, and then disconnect it from the
network, freeing up the PIP.
For example (unrealistic, since a real ALU LUT has a larger size and
service bits in the middle, etc.), the addition function of A and B when
A = 1 is converted from the general case (A isn't a constant and B isn't a
constant) to a special case:
0110 -> 0011

The renaming of ALU ports for ADD and SUB modes has also been
removed—this has already been done in the chip database as a fixed
change to the ALU LUT.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

* Gowin. Fix the style.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>

---------

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2025-08-29 16:58:26 +02:00