Merge branch 'master' into netgen-1.5

move to the start index before relinking the sorted entries.  That
will cause properties to be lost whenever the start index is greater
than zero.  Not sure why this hasn't been caught previously, or
whether other errors are involved here.

VERSION

@@ -1 +1 @@
-1.5.252
+1.5.263

base/ext.c

@@ -31,6 +31,8 @@ the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
 #include "print.h"
 #include "hash.h"
 
+static int invlambda = 100;	/* Used in sim and prm files */
+
 void extCell(char *name, int filenum)
 {
   struct nlist *tp, *tp2;
@@ -450,7 +452,8 @@ void simCell(char *name, int filenum)
   struct nlist *tp, *tp2;
   struct objlist *ob, *ob2;
   char FileName[500], simclass;
-  short i;
+  char writeLine[1024], paramString[128];
+  short i, p, mult;
   double l, w, v;
 
   tp = LookupCellFile(name, filenum);
@@ -478,9 +481,9 @@ void simCell(char *name, int filenum)
   }
 
   /* print out header list */
-  /* distance units are multiplied by 100 (distances are in um) */
+  /* distance units are multiplied by invlambda */
 
-  FlushString("| units: 100    tech: scmos\n");
+  FlushString("| units: %d    tech: scmos\n", 100 * invlambda);
 
   /* now run through cell's contents, print instances */
   for (ob = tp->cell; ob != NULL; ob = ob->next) {
@@ -516,13 +519,17 @@ void simCell(char *name, int filenum)
 	 case CLASS_NPN:
 	    simclass = 'b';
 	    break;	
-	 default:
+	 case CLASS_SUBCKT:
+	 case CLASS_MODULE:
 	    simclass = 'x';
 	    break;	
+	 default:
+	    simclass = '|';
+	    break;	
       }
 
       if (simclass != 'x')
-         FlushString("%c", simclass);
+	 FlushString("%c", simclass);
 
       switch (tp2->class) {
 	 case CLASS_NMOS: case CLASS_NMOS4:
@@ -590,6 +597,115 @@ void simCell(char *name, int filenum)
 	    FlushString(" %g\n", v);   
 	    break;
 
+	 case CLASS_MODULE:
+	    *writeLine = 'x';
+	    *(writeLine + 1) = '\0';
+	    mult = 1;
+
+	    /* Important---Need to look up the cell definition;  if
+	     * the first pin is "drain" then it is a FET, and pins
+	     * get swapped from D-G-S-B to G-S-D-B.  Source and drain
+	     * are treated here as equivalent because the .sim format
+	     * has no concept of an asymmetric source and drain.
+	     */
+	    ob2 = tp2->cell;
+	    if ((*matchfunc)(ob2->next->name, "gate"))
+	    {
+	      strcat(writeLine, " ");
+	      strcat(writeLine, NodeAlias(tp, ob->next));
+	      strcat(writeLine, " ");
+	      strcat(writeLine, NodeAlias(tp, ob));
+	      ob2 = ob->next->next;
+	    }
+	    else
+	      ob2 = ob;
+
+	    while (ob2 != NULL) {
+	      strcat(writeLine, " ");
+	      strcat(writeLine, NodeAlias(tp, ob2));
+	      ob2 = ob2->next;
+	      if ((ob2 == NULL) || (ob2->type <= FIRSTPIN)) break;
+	    }
+
+	    if (ob2 && ob2->type == PROPERTY) {
+	       struct valuelist *vl;
+	       /* Only known parameters are L, W, X, and Y */
+	       for (p = 0;; p++) {
+	          vl = (struct valuelist *)(&(ob2->instance.props[p]));
+		  if (vl->type == PROP_ENDLIST) {
+	             strcat(writeLine, " l=1");   
+		     break;
+		  }
+		  else if ((*matchfunc)(vl->key, "L")) {
+	             v = vl->value.dval;
+	             sprintf(paramString, " l=%d", (int)(0.5 + (v * invlambda)));   
+	             strcat(writeLine, paramString);
+		     break;
+		  }
+	       }
+	       for (p = 0;; p++) {
+	          vl = (struct valuelist *)(&(ob2->instance.props[p]));
+		  if (vl->type == PROP_ENDLIST) {
+	             strcat(writeLine, " w=1");   
+		     break;
+		  }
+		  else if ((*matchfunc)(vl->key, "W")) {
+	             v = vl->value.dval;
+	             sprintf(paramString, " w=%d", (int)(0.5 + (v * invlambda)));   
+	             strcat(writeLine, paramString);
+		     break;
+		  }
+	       }
+	       for (p = 0;; p++) {
+	          vl = (struct valuelist *)(&(ob2->instance.props[p]));
+		  if (vl->type == PROP_ENDLIST) {
+	             strcat(writeLine, " x=0");   
+		     break;
+		  }
+		  else if ((*matchfunc)(vl->key, "X")) {
+	             i = vl->value.ival;
+	             sprintf(paramString, " x=%d", i);
+	             strcat(writeLine, paramString);
+		     break;
+		  }
+	       }
+	       for (p = 0;; p++) {
+	          vl = (struct valuelist *)(&(ob2->instance.props[p]));
+		  if (vl->type == PROP_ENDLIST) {
+	             strcat(writeLine, " y=0");   
+		     break;
+		  }
+		  else if ((*matchfunc)(vl->key, "Y")) {
+	             i = vl->value.ival;
+	             sprintf(paramString, " y=%d", i);
+	             strcat(writeLine, paramString);
+		  }
+	       }
+	       for (p = 0;; p++) {
+	          vl = (struct valuelist *)(&(ob2->instance.props[p]));
+		  if (vl->type == PROP_ENDLIST) {
+		     break;
+		  }
+		  else if ((*matchfunc)(vl->key, "M")) {
+		     if (vl->type == PROP_INTEGER)
+	                mult = vl->value.ival;
+		     else
+	                mult = vl->value.dval;
+		  }
+	       }
+	    }
+	    strcat(writeLine, " ");
+	    strcat(writeLine, tp2->name);   
+	    strcat(writeLine, "\n");   
+
+	    /* Multiple instances (M != 1) are written multiple times.
+	     * NF is ignored in favor of having a single device with
+	     * the total width.
+	     */
+	    for (i = 0; i < mult; i++)
+		FlushString(writeLine);
+	    break;
+
 	 default:
 	    FlushString("| unhandled component %s\n", tp2->name);   
 	    break;
@@ -626,6 +742,181 @@ int StrIsInt(char *s)
     return (1);
 }
 
+/*------------------------------------------------------*/
+/* Read a .prm format file.  This is specifically to	*/
+/* get the "device" lines that indicate how a SPICE	*/
+/* subcircuit model or a .sim "x" record needs to be	*/
+/* translated into a specific component type like a	*/
+/* FET, diode, resistor, etc.				*/
+/*------------------------------------------------------*/
+
+char *ReadPrm(char *fname, int *fnum)
+{
+  int filenum;
+  struct keyvalue *kvlist = NULL;
+  struct nlist *tp;
+
+  if ((filenum = OpenParseFile(fname, *fnum)) < 0) {
+    char name[MAX_STR_LEN];
+
+    SetExtension(name, fname, PRM_EXTENSION);
+    if (OpenParseFile(name, *fnum) < 0) {
+      Printf("Error in prm file read: No file %s\n",name);
+      *fnum = filenum;
+      return NULL;
+    }    
+  }
+
+  /* Make sure all .prm file reading is case INsensitive */
+  /* This is because the only reason to read a PRM file	 */
+  /* is to find all the subcircuit device types	so that	 */
+  /* a SPICE file can be read and a SIM file written.	 */
+
+  matchfunc = matchnocase;
+  matchintfunc = matchfile;
+  hashfunc = hashnocase;
+
+  CellDef(fname, filenum);
+
+  while (!EndParseFile()) {
+    char devicename[MAX_STR_LEN];
+    SkipTok(NULL);
+
+    if (EndParseFile()) break;
+    if (nexttok[0] == ';') continue;		/* Comment line */
+    else if (nexttok[0] == '\0') continue;	/* Blank line */
+    else if (match(nexttok, "lambda")) {
+      SkipTok(NULL);
+      invlambda = (int)(0.5 + (1.0 / atof(nexttok)));
+      SkipNewLine(NULL); /* skip any attributes */
+    }
+    else if (match(nexttok, "device")) {
+      SkipTok(NULL);
+      if (match(nexttok, "nfet")) {
+	 SkipTok(NULL);
+	 strcpy(devicename, nexttok);
+	 /* Create 4-terminal nfet subcircuit device record */
+	 if (LookupCellFile(devicename, filenum) == NULL) {
+	     CellDef(devicename, filenum);
+	     Port("drain");
+	     Port("gate");
+	     Port("source");
+	     Port("bulk");
+	     PropertyDouble(devicename, filenum, "l", 0.01, 0.0);
+	     PropertyDouble(devicename, filenum, "w", 0.01, 0.0);
+	     PropertyInteger(devicename, filenum, "nf", 0, 1);
+	     PropertyInteger(devicename, filenum, "m", 0, 1);
+	     SetClass(CLASS_MODULE);
+	     EndCell();
+	     ReopenCellDef(fname, filenum);
+	 }
+         LinkProperties(devicename, kvlist);
+         SkipNewLine(NULL); /* skip any attributes */
+      }
+      else if (match(nexttok, "pfet")) {
+	 SkipTok(NULL);
+	 strcpy(devicename, nexttok);
+	 /* Create 4-terminal pfet subcircuit device record */
+	 if (LookupCellFile(devicename, filenum) == NULL) {
+	     CellDef(devicename, filenum);
+	     Port("drain");
+	     Port("gate");
+	     Port("source");
+	     Port("well");
+	     PropertyDouble(devicename, filenum, "l", 0.01, 0.0);
+	     PropertyDouble(devicename, filenum, "w", 0.01, 0.0);
+	     PropertyInteger(devicename, filenum, "nf", 0, 1);
+	     PropertyInteger(devicename, filenum, "m", 0, 1);
+	     SetClass(CLASS_MODULE);
+	     EndCell();
+	     ReopenCellDef(fname, filenum);
+	 }
+         LinkProperties(devicename, kvlist);
+         SkipNewLine(NULL); /* skip various attributes */
+      }
+      else if (match(nexttok, "resistor")) {
+	 SkipTok(NULL);
+	 strcpy(devicename, nexttok);
+	 /* Resistor device has additional record for the value */
+	 /* (Need to do something with this. . . ?) */
+	 SkipTok(NULL);
+	 /* Create resistor subcircuit device record */
+         if (LookupCellFile(devicename, filenum) == NULL) {
+            CellDef(devicename, filenum);
+            Port("end_a");
+            Port("end_b");
+            PropertyDouble(devicename, filenum, "value", 0.01, 0.0);
+	    PropertyDouble(devicename, filenum, "l", 0.01, 0.0);
+	    PropertyDouble(devicename, filenum, "w", 0.01, 0.0);
+	    PropertyInteger(devicename, filenum, "m", 0, 1);
+            SetClass(CLASS_MODULE);
+            EndCell();
+            ReopenCellDef(fname, filenum);
+         }
+	 LinkProperties(devicename, kvlist);
+         SkipNewLine(NULL); /* skip various attributes */
+      }
+      else if (match(nexttok, "capacitor")) {
+	 SkipTok(NULL);
+	 strcpy(devicename, nexttok);
+	 /* Capacitor device has additional record for the value */
+	 /* (Need to do something with this. . . ?) */
+	 SkipTok(NULL);
+	 /* Create capacitor subcircuit device record */
+         if (LookupCellFile(devicename, filenum) == NULL) {
+            CellDef(devicename, filenum);
+            Port("top");
+            Port("bottom");
+            PropertyDouble(devicename, filenum, "value", 0.01, 0.0);
+	    PropertyDouble(devicename, filenum, "l", 0.01, 0.0);
+	    PropertyDouble(devicename, filenum, "w", 0.01, 0.0);
+	    PropertyInteger(devicename, filenum, "m", 0, 1);
+            SetClass(CLASS_MODULE);
+            EndCell();
+            ReopenCellDef(fname, filenum);  /* Reopen */
+         }
+	 LinkProperties(devicename, kvlist);
+         SkipNewLine(NULL);
+      }
+      else if (match(nexttok, "diode")) {
+	 SkipTok(NULL);
+	 strcpy(devicename, nexttok);
+	 /* Create diode subcircuit device record */
+         if (LookupCellFile(devicename, filenum) == NULL) {
+            CellDef(devicename, filenum);
+            Port("anode");
+            Port("cathode");
+	    PropertyInteger(devicename, filenum, "m", 0, 1);
+            SetClass(CLASS_MODULE);
+            EndCell();
+            ReopenCellDef(fname, filenum);  /* Reopen */
+         }
+	 LinkProperties(devicename, kvlist);
+         SkipNewLine(NULL);
+      }
+      else {
+	Printf("Unknown device type in .prm: '%s'\n", nexttok);
+        InputParseError(stderr);
+        SkipNewLine(NULL);
+      }
+    }
+    else {
+      /* Could spell out all the keywords used in .prm files    */
+      /* but probably not worth the effort.                     */
+      SkipNewLine(NULL);
+    }
+    DeleteProperties(&kvlist);
+  }
+  EndCell();
+  CloseParseFile();
+
+  tp = LookupCellFile(fname, filenum);
+  if (tp) tp->flags |= CELL_TOP;
+
+  *fnum = filenum;
+  return fname;
+}
+
 /*-------------------------*/
 /* Read a .sim format file */
 /*-------------------------*/
@@ -644,7 +935,7 @@ char *ReadSim(char *fname, int *fnum)
 
     SetExtension(name, fname, SIM_EXTENSION);
     if (OpenParseFile(name, *fnum) < 0) {
-      Printf("Error in ext file read: No file %s\n",name);
+      Printf("Error in sim file read: No file %s\n",name);
       *fnum = filenum;
       return NULL;
     }    
@@ -847,7 +1138,7 @@ char *ReadSim(char *fname, int *fnum)
     }
     else if (match(nexttok, "r")) {	/* 2-port resistors */
       if (IgnoreRC) {
-	/* ignore all capacitances */
+	/* ignore all resistances */
 	SkipNewLine(NULL);
       }
       else {

base/flatten.c

@@ -136,17 +136,16 @@ void flattenCell(char *name, int file)
 	    ob2 = ob2->next;
 	}
     
-
       /* delete all port elements from child */
       while (IsPort(ChildObjList)) {
 	/* delete all ports at beginning of list */
 	if (Debug) Printf("deleting leading port from child\n");
 	tmp = ChildObjList->next;
 	FreeObjectAndHash(ChildObjList, ChildCell);
-	ChildObjList = tmp;
+        if ((ChildObjList = tmp) == NULL) break;
       }
       tmp = ChildObjList;
-      while (tmp->next != NULL) {
+      while (tmp && (tmp->next != NULL)) {
 	if (IsPort(tmp->next)) {
 	  ob2 = (tmp->next)->next;
 	  if (Debug) Printf("deleting a port from child\n");
@@ -536,11 +535,10 @@ int flattenInstancesOf(char *name, int fnum, char *instance)
 
          /* Do property inheritance */
 
-         /* NOTE:  Need to do:  Check properties for M > 1 and decrement
-          * and repeat without moving CurrentProp
-          */
-
          if (CurrentProp) {
+	    int i, mval;
+	    struct valuelist *kv;
+
             for (ob2 = ChildStart; ob2 != NULL; ob2=ob2->next) {
 
 	       /* If the parent cell has properties to declare, then	*/
@@ -548,10 +546,49 @@ int flattenInstancesOf(char *name, int fnum, char *instance)
 	       /* spiceparams dictionary is active (during file		*/
 	       /* reading only).					*/
 
-	       if (ob2->type == PROPERTY)
+	       if (ob2->type == PROPERTY) {
 		  ReduceExpressions(ob2, CurrentProp, ChildCell,
 				(spiceparams.hashtab == NULL) ? 0 : 1);
-            }
+	       }
+	    }
+
+	    /* Check for property M.  If it exists and is greater than	*/
+	    /* one, reduce it and repeat;  i.e., generate multiple	*/
+	    /* child instances to match the M value.  Probably this	*/
+	    /* could be done quicker by just creating a new property	*/
+	    /* M for a single child.					*/
+
+	    mval = 0;
+	    for (i = 0; ; i++) {
+	       kv = &(CurrentProp->instance.props[i]);
+	       if (kv->type == PROP_ENDLIST) break;
+	       if ((*matchfunc)(kv->key, "M")) {
+		   if (kv->type == PROP_INTEGER) {
+		      mval = kv->value.ival;
+		      kv->value.ival = mval - 1;
+		      break;
+		   }
+		   else if (kv->type == PROP_DOUBLE) {
+		      mval = (int)kv->value.dval;
+		      kv->value.dval = (double)mval - 1;
+		      break;
+		   }
+	       }
+	    }
+	    if (mval > 1) {
+	       /* Put the child cell at the start of ChildObjList */
+	       if (ChildEnd) {
+	          ChildEnd->next = ChildObjList;
+	          ChildObjList = ChildStart;
+	
+	          /* Continue without moving CurrentProp */
+		  /* Note that if ChildEnd is NULL then the child cell
+		   * is optimized out and there is no need to do it
+		   * M times.
+		   */
+	          continue;
+	       }
+	    }
 
             /* Repeat for each property record, as each property represents a
              * unique instance that must be flattened individually.
@@ -1177,7 +1214,6 @@ int UniquePins(char *name, int filenum)
    firstport = (struct objlist **)CALLOC(maxnode + 1, sizeof(struct objlist *));
 
    portcount = FIRSTPIN;
-   lob = NULL;
    for (ob = ThisCell->cell; ob != NULL; ob = ob->next) {
       if (ob->type != PORT) break;
       if (ob->node > 0) {
@@ -1188,16 +1224,12 @@ int UniquePins(char *name, int filenum)
 			firstport[ob->node]->name, ThisCell->name, ThisCell->file);
 	       /* Do not count this as a duplicate pin. */
 	       nodecount[ob->node]--;
-	       /* Move the pin adjacent to the one it is shorted to (if it	
-		* isn't already);  this will make the work of MatchPins() easier.
+	       /* Note:  Previously there was code here to move the shorted port
+		* next to the pin it is shorted to.  This causes the cell def pins
+		* to become scrambled with respect to the pin order of its instances.
+		* Removed the code 9/1/2023.  But---Not sure if any code depends
+		* on shorted pins being adjacent.
 		*/
-	       if (firstport[ob->node]->next != ob) {
-	          lob->next = ob->next;
-	          ob->next = firstport[ob->node]->next;
-		  firstport[ob->node]->next = ob;
-	          ob = lob;
-	       }
-	       lob = ob;
 	       continue;
 	    }
 	    else {
@@ -1218,7 +1250,6 @@ int UniquePins(char *name, int filenum)
 	 }
       }
       portcount++;
-      lob = ob;
    }
 
    if (needscleanup)
@@ -1600,6 +1631,7 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
     ECompList *list0X, *listX0;
     int hascontents1, hascontents2;
     int match, modified = 0;
+    int not_top;
 
     if (file1 == -1)
 	tc1 = LookupCell(name1);
@@ -1870,6 +1902,8 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
     // Remove non-matching zero-value devices.  This can
     // be done on a per-instance basis.
 
+    not_top = (PeekCompareQueueTop(NULL, NULL, NULL, NULL) == -1) ? FALSE : TRUE;
+
     ecomp = (ECompare *)HashFirst(&compdict);
     while (ecomp != NULL) {
 	if ((ecomp->num1 != ecomp->num2) && (ecomp->cell1 != NULL) &&
@@ -1916,6 +1950,33 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
 						    break;
 					    }
 					}
+
+					/* Do NOT remove shorting devices that	*/
+					/* connect two ports.  Otherwise the	*/
+					/* port lists get screwed up.  It is	*/
+					/* better in that case to force the	*/
+					/* cells to be declared mismatched.	*/
+					/* This is ignored for a top-level cell	*/
+					/* because it will just show up as a	*/
+					/* port mismatch error as it should.	*/
+
+					if ((not_top == TRUE) &&
+						(ecomp->cell1->class != CLASS_ISOURCE)) {
+					    int found1 = FALSE;
+					    int found2 = FALSE;
+					    for (ob2 = tc1->cell; ob2; ob2 = ob2->next) {
+						if (!IsPort(ob2)) break;
+						else if (ob2->node == node1)
+						    found1 = TRUE;
+						else if (ob2->node == node2)
+						    found2 = TRUE;
+						if (found1 && found2) {
+						    found = FALSE;
+						    break;
+						}
+					    }
+					}
+
 					if (found) break;
 				    }
 				    if (found) {
@@ -2037,6 +2098,27 @@ PrematchLists(char *name1, int file1, char *name2, int file2)
 						    break;
 					    }
 					}
+
+					/* (See comments above about removing shorts */
+					/* between two ports.)			     */
+
+					if ((not_top == TRUE) &&
+						(ecomp->cell2->class != CLASS_ISOURCE)) {
+					    int found1 = FALSE;
+					    int found2 = FALSE;
+					    for (ob1 = tc2->cell; ob1; ob1 = ob1->next) {
+						if (!IsPort(ob1))  break;
+						else if (ob1->node == node1)
+						    found1 = TRUE;
+						else if (ob1->node == node2)
+						    found2 = TRUE;
+						if (found1 && found2) {
+						    found = FALSE;
+						    break;
+						}
+					    }
+					}
+					
 					if (found) break;
 				    }
 				    if (found) {

base/netcmp.c

@@ -3773,20 +3773,23 @@ int CreateCompareQueue(char *name1, int file1, char *name2, int file2)
    return 0;
 }
 
-/*----------------------------------------------*/
-/* Read the top of the compare queue, but do	*/
-/* not alter the stack.				*/
-/*----------------------------------------------*/
+/*----------------------------------------------------------------*/
+/* Read the top of the compare queue, but do not alter the stack. */
+/* Return -1 if there is no compare queue.  This is a way to	  */
+/* check if the current cells being checked are the topmost in	  */
+/* the queue.  Call with all NULL values for a quick check for a  */
+/* top-level compare.						  */
+/*----------------------------------------------------------------*/
 
 int PeekCompareQueueTop(char **name1, int *file1, char **name2, int *file2)
 {
    if (CompareQueue == NULL)
       return -1;
 
-   *name1 = CompareQueue->class1;
-   *file1 = CompareQueue->file1;
-   *name2 = CompareQueue->class2;
-   *file2 = CompareQueue->file2;
+   if (name1) *name1 = CompareQueue->class1;
+   if (file1) *file1 = CompareQueue->file1;
+   if (name2) *name2 = CompareQueue->class2;
+   if (file2) *file2 = CompareQueue->file2;
 
    return 0;
 }
@@ -4328,6 +4331,7 @@ void series_sort(struct objlist *ob1, struct nlist *tp1, int idx1, int run)
 
    // Re-sort list
    obp = ob1;
+   for (i = 0; i < idx1; i++) obp = obp->next;
    for (i = 0; i < run; i++) {
       obp->next = proplist[i].ob;
       obp = obp->next;
@@ -4531,6 +4535,7 @@ void parallel_sort(struct objlist *ob1, struct nlist *tp1, int idx1, int run)
 
    // Re-sort list
    obp = ob1;
+   for (i = 0; i < idx1; i++) obp = obp->next;
    for (i = 0; i < run; i++) {
       obp->next = proplist[i].ob;
       obp = obp->next;
@@ -5026,21 +5031,30 @@ int PropertyOptimize(struct objlist *ob, struct nlist *tp, int run, int series,
 	       switch(vl->type) {
 		  case PROP_DOUBLE:
 		  case PROP_VALUE:
-		     dval = 2 * fabs(vl->value.dval - vl2->value.dval)
+	       	     if ((vl2->type == PROP_DOUBLE) || (vl2->type == PROP_VALUE)) {
+			dval = 2 * fabs(vl->value.dval - vl2->value.dval)
 				/ (vl->value.dval + vl2->value.dval);
-		     if (dval <= kl->slop.dval) pmatch++;
+			if (dval <= kl->slop.dval) pmatch++;
+		     }
 		     break;
 		  case PROP_INTEGER:
-		     ival = abs(vl->value.ival - vl2->value.ival);
-		     if (ival <= kl->slop.ival) pmatch++; 
+		     if (vl2->type == PROP_INTEGER) {
+			ival = abs(vl->value.ival - vl2->value.ival);
+			if (ival <= kl->slop.ival) pmatch++; 
+		     }
 		     break;
 		  case PROP_STRING:
-		     if ((*matchfunc)(vl->value.string, vl2->value.string)) pmatch++;
+		     if (vl2->type == PROP_STRING) {
+			if ((*matchfunc)(vl->value.string, vl2->value.string)) pmatch++;
+		     }
 		     break;
 
-		  /* will not attempt to match expressions, but it could
+		  /* Will not attempt to match expressions, but it could
 		   * be done with some minor effort by matching each
 		   * stack token and comparing those that are strings.
+		   * Likewise, will not attempt to match properties
+		   * whose types are mismatched, but they could be
+		   * promoted here.
 		   */
 	       }
 	    }
@@ -7428,6 +7442,8 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
    int result = 1, haspins = 0, notempty = 0;
    int hasproxy1 = 0, hasproxy2 = 0;
    int needclean1 = 0, needclean2 = 0;
+   int nomatch = 0;
+   int *correspond;
    char *ostr;
 #ifdef TCL_NETGEN
    Tcl_Obj *mlist, *plist1, *plist2;
@@ -7519,58 +7535,77 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
 		     obp = N2->object;
 		     j = 0;
 	             for (ob2 = tc2->cell; ob2 != NULL; ob2 = ob2->next, j++) {
+			nomatch = FALSE;
 	          	if ((IsPort(ob2)) && (ob2->node == obp->node)) {
 			   if (Debug == 0) {
 			      for (m = 0; m < left_col_end; m++) *(ostr + m) = ' ';
 			      for (m = left_col_end + 1; m < right_col_end; m++) *(ostr + m) = ' ';
 			      snprintf(ostr, left_col_end, "%s", ob1->name);
-			      if ((*matchfunc)(ob1->name, ob2->name))
+			   }
+			   if ((*matchfunc)(ob1->name, ob2->name)) {
+			      if (Debug == 0)
 			         snprintf(ostr + left_col_end + 1, left_col_end, "%s", ob2->name);
-			      else {
-				 /* Check remainder of ports to see if there is a name match on the
-				  * same net number (multiple ports tied to the same net)
-				  */
-				 struct objlist *ob3;
-				 for (ob3 = ob2->next, ++j; ob3 != NULL; ob3 = ob3->next, j++) {
-				     if ((IsPort(ob3)) && (ob3->node == ob2->node)) {
-					if ((*matchfunc)(ob3->name, ob1->name)) {
-					   ob2 = ob3;
+			   }
+			   else {
+			      /* Check remainder of ports to see if there is a name match on the
+			       * same net number (multiple ports tied to the same net)
+			       */
+			      struct objlist *ob3;
+			      for (ob3 = ob2->next, ++j; ob3 != NULL; ob3 = ob3->next, j++) {
+				  if ((IsPort(ob3)) && (ob3->node == ob2->node)) {
+				     if ((*matchfunc)(ob3->name, ob1->name)) {
+				        ob2 = ob3;
+					if (Debug == 0)
 			         	   snprintf(ostr + left_col_end + 1, left_col_end, "%s", ob2->name);
-					   break;
-					}
+					break;
 				     }
-				     else {
-					ob3 = NULL;
-					break;	/* All pins w/the same node should be together */
-				     }
-				 }
-				 if (ob3 == NULL) {
+				  }
+				  else {
+				     ob3 = NULL;
+				     break;	/* All pins w/the same node should be together */
+				  }
+			      }
+			      if (ob3 == NULL) {
+				 if (Debug == 0) {
 				    if (ob2->model.port == -1)
 				       snprintf(ostr + left_col_end + 1, left_col_end, "%s **Mismatch**", ob2->name);
 				    else
 				       snprintf(ostr + left_col_end + 1, left_col_end, "(no matching pin)");
-				    /* Pins with different names are on different nets,
-				     * so this should trigger an error return code.
-				     */
-				    result = 0;
 				 }
+				 nomatch = TRUE;
+				 /* Pins with different names are on different nets,
+				  * so this should trigger an error return code.
+				  */
+				 result = 0;
 			      }
+			   }
+
+			   if (Debug == 0) {
 			      for (m = 0; m < right_col_end + 1; m++)
 				 if (*(ostr + m) == '\0') *(ostr + m) = ' ';
 			      Fprintf(stdout, ostr);
 			   }
+			   else if (nomatch) {
+			      Fprintf(stderr, "No matching pin in cell %s for "
+					"cell %s pin %s\n",
+					tc2->name, tc1->name, ob1->name);
+			   }
 			   else {
 			      Fprintf(stdout, "Circuit %s port %d \"%s\""
 					" = cell %s port %d \"%s\"\n",
-					tc1->name, i, obn->name,
-					tc2->name, j, obp->name);
+					tc1->name, i, ob1->name,
+					tc2->name, j, ob2->name);
 			   }
 #ifdef TCL_NETGEN
 			   if (dolist) {
 		              Tcl_ListObjAppendElement(netgeninterp, plist1,
-					Tcl_NewStringObj(obn->name, -1));
-		              Tcl_ListObjAppendElement(netgeninterp, plist2,
-					Tcl_NewStringObj(obp->name, -1));
+					Tcl_NewStringObj(ob1->name, -1));
+			      if (nomatch)
+		 		 Tcl_ListObjAppendElement(netgeninterp, plist2,
+					Tcl_NewStringObj("(no matching pin)", -1));
+			      else
+				 Tcl_ListObjAppendElement(netgeninterp, plist2,
+					Tcl_NewStringObj(ob2->name, -1));
 			   }
 #endif
 			   ob2->model.port = i;		/* save order */
@@ -7681,6 +7716,8 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
    /* legal SPICE.						*/
 
    ob1 = tc1->cell;
+
+   correspond = (int *)CALLOC((tc1->nodename_cache_maxnodenum + 1), sizeof(int));
   
    for (i = 0; i < numorig; i++) {
       bangptr1 = strrchr(ob1->name, '!');
@@ -7723,7 +7760,7 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
 			(tc2->flags & CELL_PLACEHOLDER)) ||
 			(NodeClasses == NULL))) {
 
-	          ob2->model.port = i;		/* save order */
+	          ob2->model.port = i;			/* save order */
 	          *(cover + i) = (char)1;
 
 	          if (Debug == 0) {
@@ -7752,6 +7789,63 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
 	          if (bangptr2) *bangptr2 = '!';
 		  break;
 	       }
+	       else if ((ob1->node != -1) && (ob2->node != -1)) {
+		  /* Check for the case of ports on both sides being shorted
+		   * together.  That means that the nodes on both sides connect
+		   * only to ports, that they connect to the same number of ports,
+		   * and that each port pair has a matching name.
+		   */
+		  int onlyports = 1;
+		  struct objlist *oba, *obb;
+		  for (oba = tc1->cell; oba != NULL; oba = oba->next) {
+		     if ((oba->node == ob1->node) && (oba->type != PORT)) {
+			onlyports = 0;
+			break;
+		     } 
+		  }
+		  if (onlyports) {
+		     for (obb = tc2->cell; obb != NULL; obb = obb->next) {
+		        if ((obb->node == ob2->node) && (obb->type != PORT)) {
+			   onlyports = 0;
+			   break;
+		        } 
+		     }
+		  }
+		  if (onlyports) {
+		     if ((correspond[ob1->node] == 0) || (correspond[ob1->node] == ob2->node)) {
+
+		        correspond[ob1->node] = ob2->node;	/* remember corresponding node */
+	                ob2->model.port = i;			/* save order */
+	                *(cover + i) = (char)1;
+
+	                if (Debug == 0) {
+		           for (m = 0; m < left_col_end; m++) *(ostr + m) = ' ';
+		           for (m = left_col_end + 1; m < right_col_end; m++) *(ostr + m) = ' ';
+		           snprintf(ostr, left_col_end, "%s", ob1->name);
+		           snprintf(ostr + left_col_end + 1, left_col_end, "%s", ob2->name);
+		           for (m = 0; m < right_col_end + 1; m++)
+		              if (*(ostr + m) == '\0') *(ostr + m) = ' ';
+		           Fprintf(stdout, ostr);
+	                }
+	                else {
+		           Fprintf(stdout, "Circuit %s port %d \"%s\""
+					" = cell %s port %d \"%s\"\n",
+				tc1->name, i, ob1->name,
+				tc2->name, j, ob2->name);
+	                }
+#ifdef TCL_NETGEN
+	                if (dolist) {
+		           Tcl_ListObjAppendElement(netgeninterp, plist1,
+					Tcl_NewStringObj(ob1->name, -1));
+		           Tcl_ListObjAppendElement(netgeninterp, plist2,
+					Tcl_NewStringObj(ob2->name, -1));
+	                }
+#endif
+		     }
+	             if (bangptr2) *bangptr2 = '!';
+		     break;
+		  }
+	       }
 	    }
 	    if (bangptr2) *bangptr2 = '!';
 	    j++;
@@ -7760,6 +7854,7 @@ int MatchPins(struct nlist *tc1, struct nlist *tc2, int dolist)
       ob1 = ob1->next;
       if (bangptr1) *bangptr1 = '!';
    }
+   FREE(correspond);
 
    /* Find the end of the pin list in tc1, for adding proxy pins */
 

base/netfile.c

@@ -611,7 +611,8 @@ void SpiceTokNoNewline(void)
 }
 
 /*----------------------------------------------------------------------*/
-/* Skip to the next token, ignoring any C-style comments.		*/
+/* Skip to the next token, ignoring any C-style comments and verilog	*/
+/* "(* ... *)"-style comments.						*/
 /*----------------------------------------------------------------------*/
 
 void SkipTokComments(char *delimiter)
@@ -627,6 +628,11 @@ void SkipTokComments(char *delimiter)
 		SkipTok(delimiter);
 	    if (nexttok) SkipTok(delimiter);
 	}
+	else if (match(nexttok, "(*")) {
+	    while (nexttok && !match(nexttok, "*)"))
+		SkipTok(delimiter);
+	    if (nexttok) SkipTok(delimiter);
+	}
 	else break;
     }
 }
@@ -731,7 +737,7 @@ char *strdtok(char *pstring, char *delim1, char *delim2)
     if (*s == '\\') {
         s++;
         while (*s != '\0') {
-	    if ((*s == ' ') || (*s == '\\')) {
+	    if ((*s == ' ') || ((*s == '\\') && (*(s + 1) == '\0'))) {
 		s++;
 		break;
 	    }
@@ -880,7 +886,7 @@ char *ReadNetlist(char *fname, int *fnum)
   };
   
 #ifdef mips
-  struct filetype formats[7];
+  struct filetype formats[8];
 
   formats[0].extension = NTK_EXTENSION;
   formats[0].proc = ReadNtk;
@@ -888,14 +894,16 @@ char *ReadNetlist(char *fname, int *fnum)
   formats[1].proc = ReadExtHier;
   formats[2].extension = SIM_EXTENSION;
   formats[2].proc = ReadSim;
-  formats[3].extension = SPICE_EXTENSION;
-  formats[3].proc = ReadSpice;
-  formats[4].extension = NETGEN_EXTENSION;
-  formats[4].proc = ReadNetgenFile;
-  formats[5].extension = VERILOG_EXTENSION;
-  formats[5].proc = ReadVerilogFile;
-  formats[6].extension = NULL;
-  formats[6].proc = NULL;
+  formats[3].extension = PRM_EXTENSION;
+  formats[3].proc = ReadPrm;
+  formats[4].extension = SPICE_EXTENSION;
+  formats[4].proc = ReadSpice;
+  formats[5].extension = NETGEN_EXTENSION;
+  formats[5].proc = ReadNetgenFile;
+  formats[6].extension = VERILOG_EXTENSION;
+  formats[6].proc = ReadVerilogFile;
+  formats[7].extension = NULL;
+  formats[7].proc = NULL;
 
 #else  /* not mips (i.e. compiler with reasonable initializers) */
   
@@ -904,6 +912,7 @@ char *ReadNetlist(char *fname, int *fnum)
       {NTK_EXTENSION, ReadNtk},
       {EXT_EXTENSION, ReadExtHier},
       {SIM_EXTENSION, ReadSim},
+      {PRM_EXTENSION, ReadPrm},
       {SPICE_EXTENSION, ReadSpice},
       {SPICE_EXT2, ReadSpice},
       {SPICE_EXT3, ReadSpice},

base/netfile.h

@@ -7,6 +7,7 @@
 #define WOMBAT_EXTENSION ".wom"
 #define EXT_EXTENSION ".ext"
 #define SIM_EXTENSION ".sim"
+#define PRM_EXTENSION ".prm"
 #define SPICE_EXTENSION ".spice"
 #define SPICE_EXT2 ".spc"
 #define SPICE_EXT3 ".sp"

base/netgen.h

@@ -191,6 +191,7 @@ extern char *ReadNtk (char *fname, int *fnum);
 extern char *ReadExtHier(char *fname, int *fnum);
 extern char *ReadExtFlat(char *fname, int *fnum);
 extern char *ReadSim(char *fname, int *fnum);
+extern char *ReadPrm(char *fname, int *fnum);
 extern char *ReadSpice(char *fname, int *fnum);
 extern char *ReadSpiceLib(char *fname, int *fnum);
 extern char *ReadNetgenFile (char *fname, int *fnum);

base/verilog.c

@@ -1017,13 +1017,12 @@ void ReadVerilogFile(char *fname, int filenum, struct cellstack **CellStackPtr,
   char devtype, in_module, in_param;
   char *eqptr, *matchptr;
   struct keyvalue *kvlist = NULL;
-  char inst[MAX_STR_LEN], model[MAX_STR_LEN], instname[MAX_STR_LEN], portname[MAX_STR_LEN], pkey[MAX_STR_LEN];
+  char inst[MAX_STR_LEN], model[MAX_STR_LEN], portname[MAX_STR_LEN], pkey[MAX_STR_LEN];
   struct nlist *tp;
   struct objlist *parent, *sobj, *nobj, *lobj, *pobj, *cref;
 
   inst[MAX_STR_LEN-1] = '\0';
   model[MAX_STR_LEN-1] = '\0';
-  instname[MAX_STR_LEN-1] = '\0';
   in_module = (char)0;
   in_param = (char)0;
 
@@ -1899,12 +1898,21 @@ skip_endmodule:
 
 			if (i != -1)
 			    snprintf(nodename, MAX_STR_LEN, "%s[%d]", noderoot, i);
-			else
+			else if (lhs != NULL)
 			    strncpy(nodename, lhs->name, MAX_STR_LEN - 1);
+			else {
+			    Printf("Error:  Improper node name \"%s\".\n", noderoot);
+			    goto skip_endmodule;
+			}
 			if (j != -1)
 			    snprintf(assignname, MAX_STR_LEN, "%s[%d]", assignroot, j);
-			else
+			else if (rhs != NULL)
 			    strncpy(assignname, rhs->name, MAX_STR_LEN - 1);
+			else {
+			    Printf("Error:  Improper assignment name \"%s\".\n",
+					assignroot);
+			    goto skip_endmodule;
+			}
 
 			join(nodename, assignname);
 

tcltk/netgen.tcl.in

@@ -741,6 +741,19 @@ set auto_noexec 1       ;# don't EVER call UNIX commands w/o "shell" in front
 # Cross-Application section
 #----------------------------------------------------------------------
 
+# For use with open_pdks, set PDK_ROOT from the environment.  If no
+# such environment variable exists, check some common locations.
+
+if {[catch {set PDK_ROOT $::env(PDK_ROOT)}]} {
+    if {[file isdir /usr/local/share/pdk] == 1} {
+	set PDK_ROOT /usr/local/share/pdk
+    } elseif {[file isdir /usr/share/pdk] == 1} {
+	set PDK_ROOT /usr/share/pdk
+    } elseif {[file isdir /foss/pdk] == 1} {
+	set PDK_ROOT /foss/pdk
+    }
+}
+
 # Setup IRSIM assuming that the Tcl version is installed.
 # We do not need to rename procedure irsim to NULL because it is
 # redefined in a script, which simply overwrites the original.

tcltk/tclnetgen.c

@@ -707,11 +707,11 @@ _netgen_readnet(ClientData clientData,
     Tcl_Interp *interp, int objc, Tcl_Obj *CONST objv[])
 {
    char *formats[] = {
-      "automatic", "ext", "extflat", "sim", "ntk", "spice",
+      "automatic", "ext", "extflat", "sim", "prm", "ntk", "spice",
       "verilog", "netgen", "actel", "xilinx", NULL
    };
    enum FormatIdx {
-      AUTO_IDX, EXT_IDX, EXTFLAT_IDX, SIM_IDX, NTK_IDX,
+      AUTO_IDX, EXT_IDX, EXTFLAT_IDX, SIM_IDX, PRM_IDX, NTK_IDX,
       SPICE_IDX, VERILOG_IDX, NETGEN_IDX, ACTEL_IDX, XILINX_IDX
    };
    struct nlist *tc;
@@ -807,6 +807,9 @@ _netgen_readnet(ClientData clientData,
          case SIM_IDX:
             retstr = ReadSim(savstr, &filenum);
             break;
+         case PRM_IDX:
+            retstr = ReadPrm(savstr, &filenum);
+            break;
          case NTK_IDX:
             retstr = ReadNtk(savstr, &filenum);
             break;