marked as unneeded, so I simply removed the code rather than
debug the issue, which was that buses got the delimeters erased
for checking but never put back again. Also: Modified the verilog
reading code so that if an empty set "()" is given for a pin, then
the initial proxy, which is a single net with the name prefix
"_noconnect_", can be promoted to a bus if further processing
reveals it to be a bus and not a single-bit signal.
used when ob may be NULL. Added a check in front for ob == NULL.
Also: Changed the disconnected node alert so that it does not
mention nodes marked "port_mismatch_error". These are disconnected
by definition, will show up in the pin list, and printing them as
"disconnected pins" is just confusing to the end user.
should not be called after CreateTwoLists(). CreateTwoLists()
was being called in one case only to print the contents of the
cells, so that part was pulled out into a separate routine.
contents (previously wasn't done), and also added sorting for items with
non-matching names which have only one item in the group for each circuit
(so they must be matching in some sense). This makes the output a bit
more readable without re-enabling the compute-intensive sorting method
for non-matching entries.
print statement, and clarified the messages about non-matching
circuits at the end, all of them suggestions made by Mitch
Bailey (see issue #34 on github).
saying that pins were mismatched when pin matching was never run
accidentally resulted in pin matching not being applied to black-box
entries. This has been corrected.
pins on non-black-boxed circuits as it does not black-boxed circuits,
but specifically looking for pins that are disconnected on both sides,
since those do not appear in the node list and are not otherwise
handled. Otherwise, disconnected pins will appear to have disappeared
from the first netlist.
a final parallel or series combination needs to be done but there
are still multiple property records. The multiplier was being
incorrectly applied twice, causing an automatic mismatch in
parameter values.
swapped, so that if pin names are swapped on the top level, netgen will
report this as a final error message. Otherwise, the mismatch is only
reported back in the pin list where it is not obvious.
The algorithm is to run without exhaustive subdivision until the
last step because this is much faster. The final iteration must
be run with exhaustive subdivision on, or else it is possible to
have cells with swapped pins matching. The routines that resolve
automorphisms were setting exhaustive subdivision for the final
iteration. But simple "run converge" and "run resolve" were not.
add properties across multiple property records in the last matching
step, if there are still multiple properties and the values can be
combined. Previously, netgen had been assuming that there would only
be one property record left at this point, which is not true. This
shows up particularly for BSIM fingered devices, since "nf" is
ignored.
run to the end of the list of circuit elements. Also corrected
another issue caused by the flag to denote multiple no-connect pins,
which can be on an instance pin and so cannot share the data from the
instance record.
device with one or more no-connect pins. The flag that indicates a
no-connect pin was checked incorrectly, potentially causing obscure
and misleading property mismatch messages to be generated.
records, which were being ignored. This really only applies to
parallel subcircuits being flattened. To flatten correctly requires
that any circuit with N property records must be flattened into the
parent at least N times. To do: Must look for M > 1 records in the
properties and flatten (M - 1) additional times.
without netgen noticing---this behavior got broken by an
exception for "black box" circuits, but failed to check if the
circuit really was marked as a "black box" or not. Fixing that
revealed another issue with verilog implicit pins. Both issues
have now been corrected.
netgen. More work will be done later. Also: Removed the
derived file lvs_manager.py from the repository, and modified
the Makefile to remove it as part of "make clean".
other devices that do not have a "critical property" that determines
which properties can add together was flawed and messed up the sorting
of devices like transistors and resistors that do have a critical
property. Reworked the sorting order so that it makes sense for both
situations.
Also corrected a superficial issue with an attempt to print out an
instance name that doesn't exist. There is an underlying bug here
related to cells that have no pins and/or no contents which has not
been debugged. The fix just keeps netgen from segfaulting.
no pins at all. This overrides the default behavior of treating
empty cells as "black-box" entries, and avoids attempts to compare
cells like logo artwork.
different additive properties (like transistor width) to combine;
this is totally wrong and may have been left over from code written
before the routine was split into simple combinations (add similar
devices) and agressive combinations (e.g., add widths together).
cause inexplicable output in case of a property error by showing a
netlist topography error instead of a property error (but the output
shows that the netlists match, and there is no reporting of any
property errors). This error was discovered while implementing a
better sorting method for parallel combination. The improved method
sorts on two properties rather than one, and so should not fall into
the error where, say, devices are sorted on W but have different L
for a device like a capacitor where no "critical" property is
specified (and other similar cases, although that is a common one).
parallel and series devices. This was a fairly major error
undermining the property sorting (the case where the same number
of devices are in parallel in both circuits and need to be sorted
by, e.g., width, prior to checking for matches).
pins for enabling parallel combinations, which could cause a crash.
Added a "-force" option to "equate pins" to allow pins to be matched
even on subcircuits that did not correctly match; this was done in
conjuction with an extra option to the "lvs" command "-noflatten="
to pass a list of cellname to not be flattened even if they do not
match. This is generally discouraged, as it prevents netgen from
resolving differences between layout and schematic hierarchy, but it
can be useful for checking that the hierarchy above a certain cell
is correct, given that if a subcell is really unmatched, then its
errors will keep propagating up the top level, making additional
errors hard to diagnose.
parallel if the same pins are no-connects. These were previously not
treated as parallel because each no-connect has a unique node number,
and cells were only considered as parallel if all pins connected to
the same node numbers. This avoids issues with long-running symmetry
breaking on standard cell designs due to cells like antenna taps or
any cell that is placed without connecting it up. To do: This
makes indistinguishable certain cases, e.g., N cells in circuit 1
with pin X open vs. N cells in circuit 2 with pin X all tied together.
This could be caught during property matching.
to go into an infinite loop and fill memory until it crashes, due
to a complete pin mismatch between devices causing one device to
have its pins removed and replaced with proxy pins.
was running through the entire object linked list to find the
predecessor of a record that it had already found. Solved by simply
keeping track of the predecessor record.
file input so that pins occur first before nodes, as they do in a
SPICE netlist. Certain parts of the comparison code depend on pins
being first in the netlist, and reordering them when reading input
is easier than rewriting the rest of the code.
introduced in revision 150 can result in an incorrect result
reporting a bad match where the match is actually good (as proven
by running the full symmetry breaking on the same netlist).
Because the fast symmetry breaking is orders of magnitude faster
for large circuits, and because the false positive result appears
to be rare, I have introduced a command "symmetry" to switch
methods between fast and full. So fast symmetry breaking can be
run unless the result fails on symmetry breaking, in which case
the method can be switched to full to see if the problem is a
false positive or not. This is not an ideal solution, and some
investigation is needed to determine if there is a way to apply
fast symmetry breaking without encountering a false positive
error.
with the file number, so that it can get confused between libraries.
Also made a fix to coerce one cell class to be forced to be the
same in both circuits under some circumstances.
the top level circuits to be declared matching with no errors even
though the pins do not match. "proxy pins" are fine for subcells
to detect cases where one subcell has an unused pin and the matching
subcell does not declare it, but that should not be allowed on the
top level, as it cannot be known whether the pin is unused or not.
corrected the error statement so that it refers both to the (corrected)
left-hand side and also the portion of the right-hand side that cannot
be parsed as structural verilog.
that are not declared in the verilog netlist because they don't
connect to anything, and their presence is not required by verilog
syntax) and the printing of proxy pins created to act as placeholders
for those implicit pins. Also removed the pinting of the "disconnected
pin" messages for black-box modules (since by definition they have
disconnected pins, because black-box modules have no contents).
to include type CLASS_MODULE in the list of types to descend into,
since "module" (black-box) types need to be checked for pin
matching even if they have no contents. This allows two verilog
netlists to be compared against each other.
of the root name of the LHS net, and so would use the last root
name copied, which might have belonged to something entirely
different, or nothing at all.
from 200 to 1024. Probably this should be dynamically allocated
and expanded as needed, as it is holding names that are of
increasing length as a hierarchy is descended and the instance
prefixes appended to the name.
However, I have identified an issue that has not yet been resolved,
which is that there can be automorphisms that are potentially
broken by property matching. Currently, the automorphisms are
arbitrarily resolved, then properties are matched---and may fail
accordingly.
in an "include" statement in either SPICE or verilog. Modified pin
matching behavior to force cells in both netlists to be marked as
black-box entries if either one is marked as a black-box entry (this
may not be needed, but shouldn't do any harm, either).
Tim Edwards
Tim Edwards