without netgen noticing---this behavior got broken by an
exception for "black box" circuits, but failed to check if the
circuit really was marked as a "black box" or not. Fixing that
revealed another issue with verilog implicit pins. Both issues
have now been corrected.
file input so that pins occur first before nodes, as they do in a
SPICE netlist. Certain parts of the comparison code depend on pins
being first in the netlist, and reordering them when reading input
is easier than rewriting the rest of the code.
corrected the error statement so that it refers both to the (corrected)
left-hand side and also the portion of the right-hand side that cannot
be parsed as structural verilog.
black-box circuits, especially those coming from verilog netlists
where a pin does not need to be declared and is implicitly floating.
This prevents the need to have an explicit black-box entry for any
verilog module that may have an instance that does not declare all
the pin connections. Also corrected an error which causes mysterious
failures if a verilog netlist is read before a SPICE netlist,
because the former gets hashed case-sensitive and the latter changes
the hashing to case-insensitive. Modified to force the SPICE
netlist to be treated case-sensitive, which may cause errors, but
is consistent with the reverse order handling, and doesn't cause
unexplained errors.
long run-times even when there are no properties to check. Corrected
a problem with SPICE and verilog netlist reading which arbitrarily
replaces file extensions even when a file extension is given,
resulting in reading the wrong file.
definitions: Now correctly parses everything from the definition
name to the end of line as the definition value. Also: The
search for definitions in the body of the text does not reject
non-alphanumerics "_" and "$" in the definition name, without
which definition names containing those characters will go
unrecongized. Have not yet extended this to multi-line definition
values.
of the root name of the LHS net, and so would use the last root
name copied, which might have belonged to something entirely
different, or nothing at all.
scan structure because it is used in two different places and
would have to run a cost-prohibitive search of the cell's
object list. Also, was missing recording a bus input/output
signal from an "input" or "output" statement (as opposed to
in-line signals in the I/O list).
to bus pins over an array of instances. Takes care of the three
situations where the length of the signal bus equals the number of
instances; where the length of the signal bus is a multiple of
the number of instances; and where the number of instances is a
multiple of the length of the signal bus.
in an "include" statement in either SPICE or verilog. Modified pin
matching behavior to force cells in both netlists to be marked as
black-box entries if either one is marked as a black-box entry (this
may not be needed, but shouldn't do any harm, either).
with increment/decrement syntax at the end. Also the parser now
handles additional keywords associated with behavioral verilog
(initial, specify) and flags modules with them as black-box entries.
that affects vectors sliced across instance arrays. Can cause vector
numbers to be out-of-bounds if an instance is arrayed but each
instance is listed separately.
inline-I/O syntax with "wire" (e.g., "input wire [3:0] test")
and addressed the failure to add buses declared in inline I/O
to the list of known buses.
verilog parser. The parser should now be able to handle any
conditionals anywhere in the verilog code. Also a bug was found
in the code that handles "a = b" assignments, and corrected.
code using the backtick expression. Also expanded the parsing of
"ifdef", "ifndef", and "endif" to include "elsif" and "else". All
forms of "if" statements should now be handled, since verilog does
not define boolean expressions in ifdef operators like most languages
do.
assignment statements in verilog netlists, including assignment of
signal bundles. Also corrected handling of signal bundles in pin
connections, which had been corrected in qflow's verilog parser but
not copied back to netgen. Note that the syntax for signals multiplied
N times is still not handled.
handle verilog syntax. Also: Added SPICE voltage and current
sources as separate classes (as opposed to being converted to
subcircuits, which was how they were previously handled). That
allowed voltage sources to be checked for zero value and removed
by shorting the ends together, as was being done for zero value
resistors (note that like zero-value resistors, removal is only
done if removing the component makes a better match than leaving
it in). In particular, yosys has SPICE netlist output that
converts equality assignments ("assign a = b") into zero-value
voltage sources, so these components need to be treated as
non-physical elements.
accidentally erasing array delimiters from node names, a move that
surprisingly has no effect at all on LVS until the cell containing
the truncated nodes is flattened, at which point it causes odd and
confusing behavior that seems to have nothing to do with node names
at all.
type double before sorting (previously, property promotion was
being done after parallel sorting). Also, modified the verilog
file reading so that parameters and definitions that are numeric
are stored as numeric (not string) properties.
perfect). Given the complexities of the verilog language, the simple
strtok() tokenizer used by the SPICE parser is not sufficient. Wrote
a better tokenizer that can distinguish between whitespace and
functional tokens like parentheses, semicolons, etc., which are tokens
themselves but also token separators.
determine if a parameter is a floating-point number, integer, or
string, and set the parameter accordingly. Found an error in the
parameter comparison if the subcircuit definitions don't agree
on the type of parameter. Now all values are promoted to a single
type based on preference order (double, integer, string). Tested
on a verilog file with a primitive device type defined as a module
with its properties encoded as parameters. This successfully
matched against the SPICE primitive device.
ifndef, endif conditional statements. Pre-define the key "LVS"
for use with netgen. Also corrected some problems stemming from
the way delimiters are handled and the flexible use of whitespace
in verilog.
be in any specific order since all ports are named. Also corrected
problem with pin names not using the same string matching function
as used for nets in general (which affects the ability to match
against different bus delimiters).
some problems stemming from comparing a case-sensitive netlist
against a case-insensitive one. Verilog netlist reading does
not yet have support for macros other than "`include", and it
does not yet have support for bit vectors constructed with
braces ({}).
Tim Edwards
Alessandro De Laurenzis