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netgen
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Revised the verilog parser to correctly identify and parse 

parameters passed to instances, so that these can match critical
parameters in the SPICE netlist being compared against.
This commit is contained in:
Tim Edwards 2018-05-23 13:04:31 -04:00
parent b721cacb40
commit 534ea839c0
1 changed files with 2 additions and 8 deletions
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10
base/verilog.c
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@ -884,6 +884,7 @@ skip_endmodule:
while (nexttok != NULL) {
char *paramname;
SkipTok(VLOG_DELIMITERS2);
while (match(nexttok, "//")) {
SkipNewLine(VLOG_DELIMITERS);
@ -896,14 +897,7 @@ skip_endmodule:
// We need to look for parameters of the type ".name(value)"
SkipTok(VLOG_DELIMITERS2);
while (match(nexttok, "//")) {
SkipNewLine(VLOG_DELIMITERS);
SkipTok(VLOG_DELIMITERS2);
}
if (nexttok[0] != '.') {
Printf("Badly formed subcircuit parameter line at \"%s\"\n", nexttok);
}
if (nexttok[0] != '.') break;
else {
paramname = strsave(nexttok + 1);
SkipTok(VLOG_DELIMITERS2);