Modified the verilog reading code so that it will automatically
determine if a parameter is a floating-point number, integer, or string, and set the parameter accordingly. Found an error in the parameter comparison if the subcircuit definitions don't agree on the type of parameter. Now all values are promoted to a single type based on preference order (double, integer, string). Tested on a verilog file with a primitive device type defined as a module with its properties encoded as parameters. This successfully matched against the SPICE primitive device.
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5223011330
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036e1f0947
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@ -4625,7 +4625,7 @@ PropertyCheckMismatch(struct objlist *tp1, struct nlist *tc1,
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{
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int mismatches = 0;
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int len2, *check2;
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struct property *kl1, *kl2;
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struct property *kl1, *kl2, *klt;
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struct valuelist *vl1, *vl2;
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int i, j;
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int islop;
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@ -4797,8 +4797,27 @@ PropertyCheckMismatch(struct objlist *tp1, struct nlist *tc1,
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/* Promote properties as necessary to make sure they all match */
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if (kl1->type != vl1->type) PromoteProperty(kl1, vl1);
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if (kl2->type != vl2->type) PromoteProperty(kl2, vl2);
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if (kl1->type != vl2->type) PromoteProperty(kl1, vl2);
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if (vl1->type != kl2->type) PromoteProperty(kl2, vl1);
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/* If kl1 and kl2 types differ, choose one type to target. Prefer */
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/* double if either type is double, otherwise string. */
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if (kl1->type == PROP_DOUBLE)
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klt = kl1;
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else if (kl2->type == PROP_DOUBLE)
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klt = kl2;
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else if (kl1->type == PROP_INTEGER)
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klt = kl1;
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else if (kl2->type == PROP_INTEGER)
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klt = kl2;
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else if (kl1->type == PROP_STRING)
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klt = kl1;
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else if (kl2->type == PROP_STRING)
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klt = kl2;
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else
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klt = kl1;
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if (vl2->type != klt->type) PromoteProperty(klt, vl2);
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if (vl1->type != klt->type) PromoteProperty(klt, vl1);
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if (vl1->type != vl2->type) {
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if (do_print && (vl1->type != vl2->type)) {
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@ -4849,13 +4868,13 @@ PropertyCheckMismatch(struct objlist *tp1, struct nlist *tc1,
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if (rval != NULL) mismatches++;
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}
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else switch (kl1->type) {
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else switch (klt->type) {
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case PROP_DOUBLE:
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case PROP_VALUE:
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dval1 = vl1->value.dval;
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dval2 = vl2->value.dval;
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dslop = MAX(kl1->slop.dval, kl2->slop.dval);
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dslop = klt->slop.dval;
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pd = 2 * fabs(dval1 - dval2) / (dval1 + dval2);
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if (pd > dslop) {
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if (do_print) {
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@ -4883,7 +4902,7 @@ PropertyCheckMismatch(struct objlist *tp1, struct nlist *tc1,
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ival1 = vl1->value.ival;
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ival2 = vl2->value.ival;
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islop = MAX(kl1->slop.ival, kl2->slop.ival);
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islop = klt->slop.ival;
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if (abs(ival1 - ival2) > islop) {
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if (do_print) {
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if (mismatches == 0)
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@ -4913,7 +4932,7 @@ PropertyCheckMismatch(struct objlist *tp1, struct nlist *tc1,
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}
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break;
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case PROP_STRING:
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islop = (int)(MAX(kl1->slop.dval, kl2->slop.dval) + 0.5);
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islop = (int)(klt->slop.dval + 0.5);
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if (islop == 0) {
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if (!(*matchfunc)(vl1->value.string, vl2->value.string)) {
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if (do_print) {
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@ -375,7 +375,7 @@ void ReadVerilogFile(char *fname, int filenum, struct cellstack **CellStackPtr,
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char devtype, in_module, in_comment, in_param;
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char *eqptr, *parptr, *matchptr;
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struct keyvalue *kvlist = NULL;
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char inst[256], model[256], instname[256], portname[256];
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char inst[256], model[256], instname[256], portname[256], pkey[256];
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struct nlist *tp;
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struct objlist *parent, *sobj, *nobj, *lobj, *pobj;
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@ -540,9 +540,30 @@ void ReadVerilogFile(char *fname, int filenum, struct cellstack **CellStackPtr,
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}
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}
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else if ((eqptr = strchr(nexttok, '=')) != NULL) {
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double dval;
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*eqptr = '\0';
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// Only String properties allowed
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PropertyString(tp->name, filenum, nexttok, 0, eqptr + 1);
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/* In case the variable name is not followed by whitespace */
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if (eqptr > nexttok) strcpy(pkey, nexttok);
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eqptr++;
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// Equal sign may be followed by whitespace, in which case
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// the parameter value is the next token.
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if (strlen(eqptr) == 0) {
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SkipTok(VLOG_DELIMITERS); /* get the next token */
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eqptr = nexttok;
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}
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// Try first as a double, otherwise it's a string
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// Double value's slop defaults to 1%.
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if (ConvertStringToFloat(eqptr, &dval) == 1)
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PropertyDouble(tp->name, filenum, pkey, 0.01, dval);
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else
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PropertyString(tp->name, filenum, pkey, 0, eqptr);
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}
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else {
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/* Assume this is a keyword and save it */
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strcpy(pkey, nexttok);
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}
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}
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else {
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