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104 Commits 12 Branches 4 Tags
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13 Commits
Author SHA1 Message Date
Fischer Moseley fade794333 add initialls logic_analyzer core 2023-03-15 15:57:42 -04:00
Fischer Moseley aa2ba43e8f rename lut mem to lut ram, add to manta generator 2023-03-14 16:24:56 -04:00
Fischer Moseley 5e2f02ebd6 add linting to makefile, update bus testbenches 2023-03-14 16:24:56 -04:00
Fischer Moseley 4d9792702a clean up testbenches, add Makefile for sims 2023-03-14 16:24:56 -04:00
Fischer Moseley e022696b31 add working example for macOS bug 2023-03-14 16:24:56 -04:00
Fischer Moseley a70ba2d0a8 replace uart modules with zipcpu for testing, TX seems to misalign itself 2023-03-14 16:24:56 -04:00
Fischer Moseley 70e2bd10e7 rename, slightly patch bridge_tx 2023-03-14 16:24:56 -04:00
Fischer Moseley 70154f6904 add uart_rx module, bus seems to be working end-to-end 2023-03-14 16:24:56 -04:00
Fischer Moseley 5454ed37e9 add bus_tb, has nearly all of manta end-to-end 2023-03-14 16:24:56 -04:00
Fischer Moseley c1620871cf add lut memory and tests, still need to sort out pipelining 2023-03-14 16:24:56 -04:00
Fischer Moseley e55d919098 add in bus architecture prototypes from the last few days 2023-03-14 16:24:56 -04:00
Fischer Moseley 523b5673bc rename ila tests 2023-02-09 15:31:32 -05:00
Fischer Moseley d2bcbe2418 import from openILA 2023-02-04 12:43:00 -05:00