manta/test
Fischer Moseley a70ba2d0a8 replace uart modules with zipcpu for testing, TX seems to misalign itself 2023-03-14 16:24:56 -04:00
..
bridge_rx_tb.sv add in bus architecture prototypes from the last few days 2023-03-14 16:24:56 -04:00
bridge_tx_tb.sv add in bus architecture prototypes from the last few days 2023-03-14 16:24:56 -04:00
bus.gtkw add uart_rx module, bus seems to be working end-to-end 2023-03-14 16:24:56 -04:00
bus_tb.sv add uart_rx module, bus seems to be working end-to-end 2023-03-14 16:24:56 -04:00
fifo_tb.sv import from openILA 2023-02-04 12:43:00 -05:00
lut_mem.gtkw add bus_tb, has nearly all of manta end-to-end 2023-03-14 16:24:56 -04:00
lut_mem_tb.sv add bus_tb, has nearly all of manta end-to-end 2023-03-14 16:24:56 -04:00
manta_tb.sv rename ila tests 2023-02-09 15:31:32 -05:00
minimal_bus_tb.sv replace uart modules with zipcpu for testing, TX seems to misalign itself 2023-03-14 16:24:56 -04:00
uart_tb.sv import from openILA 2023-02-04 12:43:00 -05:00
uart_tx_tb.sv import from openILA 2023-02-04 12:43:00 -05:00