Fischer Moseley
|
b062687dc3
|
uart: use wiring.Component for internal bus
|
2026-03-11 10:23:48 -06:00 |
|
Fischer Moseley
|
9d6caec132
|
uart: remove unused bridge testbenches
|
2026-03-11 10:23:48 -06:00 |
|
Fischer Moseley
|
f4e211fe92
|
uart: fix tests for receiver and transmitter modules
|
2026-03-11 10:23:48 -06:00 |
|
Fischer Moseley
|
84172773be
|
uart: update top-level wiring in UARTInterface
|
2026-03-11 10:23:48 -06:00 |
|
Fischer Moseley
|
094bb300bd
|
uart: remove unused receive and transmit bridges
|
2026-03-11 10:23:48 -06:00 |
|
Fischer Moseley
|
49bacc86c6
|
uart: use wiring.Component instead of plain Elaborateable
|
2026-03-11 10:23:48 -06:00 |
|
Fischer Moseley
|
9211205ce8
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uart: implement stream (un)packing, tidy interfaces on COBS encoder
|
2026-03-11 10:23:48 -06:00 |
|
Fischer Moseley
|
41ad295a81
|
meta: replace Signal(1) with Signal()
|
2026-03-11 10:23:48 -06:00 |
|
Fischer Moseley
|
b6dc326018
|
uart: add skeleton of new UART RTL, add COBS from fischermoseley/cobs
|
2026-03-11 10:23:48 -06:00 |
|
Fischer Moseley
|
3bf02047d9
|
ethernet: remove obsolete tests, fix naming
|
2026-03-11 10:23:48 -06:00 |
|
Fischer Moseley
|
4dd8c77575
|
logic_analyzer: use read_block when dumping sample memory for performance
|
2026-03-11 10:23:48 -06:00 |
|
Fischer Moseley
|
907757cd28
|
ethernet: remove debug print statement
|
2026-03-11 10:23:48 -06:00 |
|
Fischer Moseley
|
3d710a6570
|
memory_core: use 32-bit instead of 16-bit data words
|
2026-03-11 10:23:48 -06:00 |
|
Fischer Moseley
|
06bfe46a3c
|
ethernet: use context manager to read generated LiteEth Verilog
|
2026-03-11 10:23:48 -06:00 |
|
Fischer Moseley
|
c83dede4f8
|
ethernet: fix host-side UDP socket leak
|
2026-03-11 10:23:48 -06:00 |
|
Fischer Moseley
|
71c54ba1e0
|
logic_analyzer: use context manager for VCD file export
|
2026-03-11 10:23:48 -06:00 |
|
Fischer Moseley
|
8d35f92848
|
logic_analyzer: fix 100% CPU wait loop in capture function
|
2026-03-11 10:23:48 -06:00 |
|
Fischer Moseley
|
d13d2c4062
|
ethernet: use EthernetMessageHeader class
|
2026-03-11 10:23:48 -06:00 |
|
Fischer Moseley
|
010397b86d
|
ethernet: fix host-side perf bug causing unneccesary retransmits
|
2026-03-11 10:23:48 -06:00 |
|
Fischer Moseley
|
bc6536ac41
|
ethernet: fix bug where single-length write request does not send response
|
2026-03-11 10:23:48 -06:00 |
|
Fischer Moseley
|
4b0176144f
|
ethernet: send write reponses, fix write request addressing bug
|
2026-03-11 10:23:48 -06:00 |
|
Fischer Moseley
|
195d5aa2a6
|
ethernet: rewrite read and write methods, fix data ordering bug
|
2026-03-11 10:23:48 -06:00 |
|
Fischer Moseley
|
09f4db144c
|
ethernet: bugfix in read transmit logic
|
2026-03-11 10:23:48 -06:00 |
|
Fischer Moseley
|
ebb8bb99cd
|
ethernet: use new bridge in EthernetInterface
|
2026-03-11 10:23:48 -06:00 |
|
Fischer Moseley
|
f2f5c622cf
|
ethernet: add first draft of new bridge
|
2026-03-11 10:23:48 -06:00 |
|
Fischer Moseley
|
a42d368d44
|
docs: add --locked to uv sync instructions
|
2026-03-11 10:23:48 -06:00 |
|
Fischer Moseley
|
3c67eaf399
|
examples: use symlinked build scripts, remove per-directory gitignores
|
2026-03-11 10:20:17 -06:00 |
|
Fischer Moseley
|
6e6cd6bfd7
|
CI: manage environment with uv
|
2026-02-25 14:57:38 -07:00 |
|
Fischer Moseley
|
1e5a247cf4
|
meta: set ruff max line length to 100 characters
This should hopefully make the Amaranth source more readable, since indentation and the `m.d.sync +=` prefix take a bit of line space.
|
2026-02-25 13:18:23 -07:00 |
|
Fischer Moseley
|
40d428614b
|
meta: add uv.lock, update installation instructions
|
2026-02-25 13:18:23 -07:00 |
|
Fischer Moseley
|
cc8e7bb08b
|
meta: use amaranth-boards from PyPI, not git
|
2026-02-25 13:18:23 -07:00 |
|
Fischer Moseley
|
10593c768e
|
logic_analyzer: fix #35, patch typos in trigger set logic
|
2025-04-08 11:18:44 -06:00 |
|
Fischer Moseley
|
b9a7e75355
|
examples: fix #37, use proper indexing in Amaranth examples
|
2025-04-06 20:15:08 -06:00 |
|
Fischer Moseley
|
9611c0b554
|
uart: fix #36, explicitly handle scientific notation in YAML config
|
2025-04-06 18:28:29 -06:00 |
|
Fischer Moseley
|
e11d9a8315
|
ci: fix typo
|
2024-12-03 22:35:16 -08:00 |
|
Fischer Moseley
|
5565a934f7
|
docs: use absolute logo path
|
2024-12-03 20:05:26 -08:00 |
|
Fischer Moseley
|
91d2f80dcc
|
meta: update pyproject.toml
|
2024-12-03 19:50:04 -08:00 |
|
Fischer Moseley
|
77b329438a
|
ci: remove unnecessary codecov.yml
|
2024-11-29 11:05:47 -07:00 |
|
Fischer Moseley
|
63efac4e92
|
ci: install manta in editable mode
|
2024-11-29 11:05:47 -07:00 |
|
Fischer Moseley
|
38808b9e5e
|
ci: show coverage report in CI, explicitly specify test directory
|
2024-11-29 11:05:47 -07:00 |
|
Fischer Moseley
|
0fb3cb0418
|
ci: explicitly specify src/ as coverage directory
|
2024-11-29 11:05:47 -07:00 |
|
Fischer Moseley
|
eddfa0bf6b
|
ci: generate XML coverage report for codecov
|
2024-11-29 11:05:47 -07:00 |
|
Fischer Moseley
|
7015be8fe9
|
meta: update package name on PyPI
|
2024-11-28 09:40:40 -08:00 |
|
Fischer Moseley
|
1e9e7081ed
|
docs: update package name in installation instructions
|
2024-11-27 21:30:12 -08:00 |
|
Fischer Moseley
|
f43732354d
|
meta: fix coverage path
|
2024-11-27 20:56:20 -08:00 |
|
Fischer Moseley
|
cb7e1e4c2a
|
meta: bump version to 1.1.0 ahead of release
|
2024-11-27 18:17:30 -08:00 |
|
Fischer Moseley
|
56223132c0
|
ci: run pre-commit on all files in CI
|
2024-11-27 19:10:52 -07:00 |
|
Fischer Moseley
|
f91f7c5fbb
|
meta: add pre-commit, commit changes it makes
|
2024-11-27 19:10:52 -07:00 |
|
Fischer Moseley
|
5759da568d
|
tests: remove redundant test_toolchains test
|
2024-11-27 19:10:52 -07:00 |
|
Fischer Moseley
|
9937269c19
|
ethernet: add individual methods for each flavor of MII
|
2024-11-27 19:10:52 -07:00 |