ethernet: rewrite read and write methods, fix data ordering bug
This commit is contained in:
Fischer Moseley
parent
09f4db144c
commit
195d5aa2a6
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@ -90,6 +90,11 @@ class EthernetInterface(Elaboratable):
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self._sink_ready = Signal()
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self._sink_valid = Signal()
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self._seq_num = 0
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self._max_retries = 3
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self._max_read_len = 126
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self._max_write_len = 126
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def _check_config(self):
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# Make sure UDP port is an integer in the range 0-65535
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if not isinstance(self._udp_port, int):
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@ -457,6 +462,51 @@ class EthernetInterface(Elaboratable):
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("o", "sgmii_link_up", sgmii_link_up),
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]
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def generate_liteeth_core(self):
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"""
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Generate a LiteEth core by calling a slightly modified form of the
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LiteEth standalone core generator. This passes the contents of the
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'ethernet' section of the Manta configuration file to LiteEth, after
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modifying it slightly.
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"""
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liteeth_config = self.to_config()
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# Randomly assign a MAC address if one is not specified in the
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# configuration. This will choose a MAC address in the Locally
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# Administered, Administratively Assigned group. Please reference:
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# https://en.wikipedia.org/wiki/MAC_address#Ranges_of_group_and_locally_administered_addresses
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if "mac_address" not in liteeth_config:
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addr = list(f"{getrandbits(48):012x}")
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addr[1] = "2"
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liteeth_config["mac_address"] = int("".join(addr), 16)
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print(liteeth_config["mac_address"])
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# Force use of DHCP
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liteeth_config["dhcp"] = True
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# Use UDP
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liteeth_config["core"] = "udp"
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# Use 32-bit words. Might be redundant, as I think using DHCP forces
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# LiteEth to use 32-bit words
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liteeth_config["data_width"] = 32
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# Add UDP port
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liteeth_config["udp_ports"] = {
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"udp0": {
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"udp_port": self._udp_port,
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"data_width": 32,
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"tx_fifo_depth": 64,
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"rx_fifo_depth": 64,
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}
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}
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# Generate the core
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from manta.ethernet.liteeth_gen import main
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return main(liteeth_config)
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def elaborate(self, platform):
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m = Module()
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@ -525,6 +575,108 @@ class EthernetInterface(Elaboratable):
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return m
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@staticmethod
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def _read_request_bytes(seq_num, addr, length):
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message = [
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(length << 16) | (seq_num << 3) | MessageTypes.READ_REQUEST,
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addr,
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]
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return b"".join([i.to_bytes(4, "little") for i in message])
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@staticmethod
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def _write_request_bytes(seq_num, addr, datas):
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message = [
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(seq_num << 3) | MessageTypes.WRITE_REQUEST,
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addr,
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*datas,
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]
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return b"".join([i.to_bytes(4, "little") for i in message])
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def _read_request(self, addr, length):
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sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
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sock.bind((self._host_ip_addr, self._udp_port))
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retry_count = 0
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while retry_count < self._max_retries:
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request = self._read_request_bytes(self._seq_num, addr, length)
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sock.sendto(request, (self._fpga_ip_addr, self._udp_port))
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data, ip_addr = sock.recvfrom(4 + (length * 4))
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if ip_addr != self._fpga_ip_addr:
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raise ValueError("Non-Manta traffic detected on this UDP port!")
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data = [
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int.from_bytes(data[i : i + 4], "little")
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for i in range(0, len(data), 4)
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]
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response_type = MessageTypes(part_select(data[0], 29, 31))
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if response_type == MessageTypes.READ_RESPONSE:
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assert len(data) == length - 1
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return data[1:]
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elif response_type == MessageTypes.NACK:
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self._seq_num = part_select(data[0], 16, 28)
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retry_count += 1
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else:
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raise ValueError("Unexpected message format received!")
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raise ValueError("Maximum number of retries exceeded!")
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def _write_request(self, addr, datas):
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sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
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sock.bind((self._host_ip_addr, self._udp_port))
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retry_count = 0
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while retry_count < self._max_retries:
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request = self._write_request_bytes(self._seq_num, addr, datas)
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sock.sendto(request, (self._fpga_ip_addr, self._udp_port))
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data, (ip_addr, port) = sock.recvfrom(4)
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assert port == self._udp_port
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if ip_addr != self._fpga_ip_addr:
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raise ValueError("Non-Manta traffic detected on this UDP port!")
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data = [
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int.from_bytes(data[i : i + 4], "little")
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for i in range(0, len(data), 4)
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]
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response_type = MessageTypes(part_select(data[0], 29, 31))
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if response_type == MessageTypes.WRITE_RESPONSE:
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return
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elif response_type == MessageTypes.NACK:
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self._seq_num = part_select(data[0], 16, 28)
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retry_count += 1
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else:
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raise ValueError("Unexpected message format received!")
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raise ValueError("Maximum number of retries exceeded!")
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def read_block(self, base_addr, length):
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data = []
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offset = 0
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while offset < length:
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chunk_size = min(self._max_read_len, length - offset)
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data += self._read_request(base_addr + offset, chunk_size)
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offset += chunk_size
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assert len(data) == length
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return data
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def write_block(self, base_addr, data):
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data_chunks = split_into_chunks(data, self._max_write_len)
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for i, chunk in enumerate(data_chunks):
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self._write_request(base_addr + (i * self._max_write_len), chunk)
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def read(self, addrs):
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"""
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Read the data stored in a set of address on Manta's internal memory.
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@ -539,30 +691,12 @@ class EthernetInterface(Elaboratable):
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if not all(isinstance(a, int) for a in addrs):
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raise TypeError("Read address must be an integer or list of integers.")
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# Send read requests, and get responses
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sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
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sock.bind((self._host_ip_addr, self._udp_port))
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chunk_size = 64 # 128
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addr_chunks = split_into_chunks(addrs, chunk_size)
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datas = []
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data = []
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seqs = parse_sequences(addrs)
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for base_addr, length in seqs:
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data += self.read_block(base_addr, length)
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for addr_chunk in addr_chunks:
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bytes_out = b""
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for addr in addr_chunk:
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bytes_out += int(0).to_bytes(4, byteorder="little")
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bytes_out += int(addr).to_bytes(2, byteorder="little")
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bytes_out += int(0).to_bytes(2, byteorder="little")
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sock.sendto(bytes_out, (self._fpga_ip_addr, self._udp_port))
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data, addr = sock.recvfrom(4 * chunk_size)
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# Split into groups of four bytes
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datas += [int.from_bytes(d, "little") for d in split_into_chunks(data, 4)]
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if len(datas) != len(addrs):
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raise ValueError("Got less data than expected from FPGA.")
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return datas
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return data
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def write(self, addrs, datas):
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"""
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@ -585,61 +719,8 @@ class EthernetInterface(Elaboratable):
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if not all(isinstance(d, int) for d in datas):
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raise TypeError("Write data must all be integers.")
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# Since the FPGA doesn't issue any responses to write requests, we
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# the host's input buffer isn't written to, and we don't need to
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# send the data as chunks as the to avoid overflowing the input buffer.
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# Encode addrs and datas into write requests
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bytes_out = b""
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for addr, data in zip(addrs, datas):
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bytes_out += int(1).to_bytes(4, byteorder="little")
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bytes_out += int(addr).to_bytes(2, byteorder="little")
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bytes_out += int(data).to_bytes(2, byteorder="little")
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sock = socket.socket(socket.AF_INET, socket.SOCK_DGRAM)
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sock.sendto(bytes_out, (self._fpga_ip_addr, self._udp_port))
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def generate_liteeth_core(self):
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"""
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Generate a LiteEth core by calling a slightly modified form of the
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LiteEth standalone core generator. This passes the contents of the
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'ethernet' section of the Manta configuration file to LiteEth, after
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modifying it slightly.
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"""
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liteeth_config = self.to_config()
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# Randomly assign a MAC address if one is not specified in the
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# configuration. This will choose a MAC address in the Locally
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# Administered, Administratively Assigned group. Please reference:
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# https://en.wikipedia.org/wiki/MAC_address#Ranges_of_group_and_locally_administered_addresses
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if "mac_address" not in liteeth_config:
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addr = list(f"{getrandbits(48):012x}")
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addr[1] = "2"
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liteeth_config["mac_address"] = int("".join(addr), 16)
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print(liteeth_config["mac_address"])
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# Force use of DHCP
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liteeth_config["dhcp"] = True
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# Use UDP
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liteeth_config["core"] = "udp"
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# Use 32-bit words. Might be redundant, as I think using DHCP forces
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# LiteEth to use 32-bit words
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liteeth_config["data_width"] = 32
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# Add UDP port
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liteeth_config["udp_ports"] = {
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"udp0": {
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"udp_port": self._udp_port,
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"data_width": 32,
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"tx_fifo_depth": 64,
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"rx_fifo_depth": 64,
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}
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}
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# Generate the core
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from manta.ethernet.liteeth_gen import main
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return main(liteeth_config)
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seqs = parse_sequences(addrs)
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offset = 0
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for base_addr, length in seqs:
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self.write_block(base_addr, datas[offset : offset + length])
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offset += length
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@ -44,7 +44,11 @@ class EthernetBridge(Elaboratable):
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# Otherwise, NACK immediately
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with m.Else():
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m.d.sync += self.data_o.eq(
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Cat(MessageTypes.NACK, seq_num_expected)
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Cat(
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C(0, unsigned(16)),
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seq_num_expected,
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MessageTypes.NACK,
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)
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)
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m.d.sync += self.valid_o.eq(1)
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m.d.sync += self.last_o.eq(1)
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@ -56,7 +60,11 @@ class EthernetBridge(Elaboratable):
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m.d.sync += read_len.eq(self.data_i[16:23] - 1)
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m.d.sync += self.data_o.eq(
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Cat(MessageTypes.READ_RESPONSE, seq_num_expected + 1)
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Cat(
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C(0, unsigned(16)),
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seq_num_expected,
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MessageTypes.READ_RESPONSE,
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)
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)
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m.d.sync += self.valid_o.eq(1)
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m.next = "READ_WAIT_FOR_ADDR"
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@ -155,7 +163,9 @@ class EthernetBridge(Elaboratable):
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with m.State("NACK_WAIT_FOR_LAST"):
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with m.If(self.last_i):
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m.d.sync += self.data_o.eq(Cat(MessageTypes.NACK, seq_num_expected))
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m.d.sync += self.data_o.eq(
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Cat(C(0, unsigned(16)), seq_num_expected, MessageTypes.NACK)
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)
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m.d.sync += self.valid_o.eq(1)
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m.d.sync += self.last_o.eq(1)
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m.d.sync += self.ready_o.eq(0)
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@ -121,6 +121,47 @@ def warn(message):
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print("Warning: " + message)
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def part_select(value, start, end):
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# Ensure the start bit is less than or equal to the end bit
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if start > end:
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raise ValueError(
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"Start bit position must be less than or equal to end bit position."
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)
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# Create a mask to isolate the bits from `start` to `end`
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mask = (1 << (end - start + 1)) - 1
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# Shift the number to the right by `start` bits and apply the mask
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return (value >> start) & mask
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def parse_sequences(numbers):
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"""
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Takes a list of integers and identifies runs of sequential numbers
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(where each number is exactly 1 more than the previous). Returns
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a list of tuples, where each tuple contains the starting number
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and the length of that sequence.
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"""
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if not numbers:
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return []
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sequences = []
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start = numbers[0]
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length = 1
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for i in range(1, len(numbers)):
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if numbers[i] == numbers[i - 1] + 1:
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length += 1
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else:
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sequences.append((start, length))
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start = numbers[i]
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length = 1
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sequences.append((start, length))
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return sequences
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def words_to_value(data):
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"""
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Takes a list of integers, interprets them as 16-bit integers, and
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