Fischer Moseley
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2c51aa9a9a
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paritally imnplement io core autogeneration
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2023-03-16 09:38:17 -04:00 |
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Fischer Moseley
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11495fca61
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refactor logic analyzer into submodules
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2023-03-15 22:43:21 -04:00 |
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Fischer Moseley
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fade794333
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add initialls logic_analyzer core
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2023-03-15 15:57:42 -04:00 |
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Fischer Moseley
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aa2ba43e8f
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rename lut mem to lut ram, add to manta generator
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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5e2f02ebd6
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add linting to makefile, update bus testbenches
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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4d9792702a
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clean up testbenches, add Makefile for sims
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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e022696b31
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add working example for macOS bug
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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a70ba2d0a8
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replace uart modules with zipcpu for testing, TX seems to misalign itself
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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70e2bd10e7
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rename, slightly patch bridge_tx
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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70154f6904
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add uart_rx module, bus seems to be working end-to-end
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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5454ed37e9
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add bus_tb, has nearly all of manta end-to-end
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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c1620871cf
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add lut memory and tests, still need to sort out pipelining
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2023-03-14 16:24:56 -04:00 |
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Fischer Moseley
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e55d919098
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add in bus architecture prototypes from the last few days
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2023-03-14 16:24:56 -04:00 |
Fischer Moseley
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523b5673bc
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rename ila tests
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2023-02-09 15:31:32 -05:00 |
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Fischer Moseley
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d2bcbe2418
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import from openILA
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2023-02-04 12:43:00 -05:00 |