examples: add nexys video uart_io_core and uart_host_to_fpga_mem

examples/verilog/nexys_video/uart_host_to_fpga_mem/.gitignore

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+!top_level.sv

examples/verilog/nexys_video/uart_host_to_fpga_mem/build.sh

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+python3 -m manta gen manta.yaml manta.v
+mkdir -p build/
+$VIVADO -mode batch -source build.tcl

examples/verilog/nexys_video/uart_host_to_fpga_mem/build.tcl

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+#!/usr/bin/tclsh
+
+set partNum xc7a200tsbg484-1
+set outputDir build
+
+read_verilog -sv [ glob *.{sv,v,svh,vh} ]
+read_xdc top_level.xdc
+
+set_part $partNum
+
+# synth
+synth_design -top top_level -part $partNum -verbose
+report_utilization -file $outputDir/post_synth_util.rpt
+report_timing_summary -file $outputDir/post_synth_timing_summary.rpt
+report_timing -file $outputDir/post_synth_timing.rpt
+
+# place
+opt_design
+place_design
+phys_opt_design
+report_utilization -file $outputDir/post_place_util.rpt
+
+report_clock_utilization -file $outputDir/clock_util.rpt
+report_timing_summary -file $outputDir/post_place_timing_summary.rpt
+report_timing -file $outputDir/post_place_timing.rpt
+
+# route design and generate bitstream
+route_design -directive Explore
+write_bitstream -force $outputDir/out.bit
+
+report_route_status -file $outputDir/post_route_status.rpt
+report_timing_summary -file $outputDir/post_route_timing_summary.rpt
+report_timing -file $outputDir/post_route_timing.rpt
+report_power -file $outputDir/post_route_power.rpt
+report_drc -file $outputDir/post_imp_drc.rpt
+write_verilog -force $outputDir/cpu_impl_netlist.v -mode timesim -sdf_anno true

examples/verilog/nexys_video/uart_host_to_fpga_mem/manta.yaml

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+---
+cores:
+  my_memory:
+    type: memory
+    mode: host_to_fpga
+    width: 8
+    depth: 256
+
+uart:
+  port: "/dev/ttyUSB1"
+  baudrate: 115200
+  clock_freq: 100000000

examples/verilog/nexys_video/uart_host_to_fpga_mem/top_level.sv

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+`default_nettype none
+`timescale 1ns / 1ps
+
+module top_level (
+	input wire clk_100mhz,
+    input wire [7:0] sw,
+    output logic [7:0] led,
+
+    input wire uart_tx_in,
+	output logic uart_rx_out);
+
+    manta manta_inst (
+        .clk(clk_100mhz),
+        .rst(0),
+
+        .rx(uart_tx_in),
+        .tx(uart_rx_out),
+
+        .user_addr(sw),
+        .user_data_out(led));
+
+endmodule
+
+`default_nettype wire

examples/verilog/nexys_video/uart_host_to_fpga_mem/top_level.xdc

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+# Clock
+set_property -dict { PACKAGE_PIN R4    IOSTANDARD LVCMOS33 } [get_ports { clk_100mhz }];
+create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk_100mhz]
+
+# UART
+set_property -dict { PACKAGE_PIN AA19  IOSTANDARD LVCMOS33 } [get_ports { uart_rx_out }];
+set_property -dict { PACKAGE_PIN V18   IOSTANDARD LVCMOS33 } [get_ports { uart_tx_in }];
+
+# LEDs
+set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS25 } [get_ports { led[0] }];
+set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS25 } [get_ports { led[1] }];
+set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS25 } [get_ports { led[2] }];
+set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS25 } [get_ports { led[3] }];
+set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS25 } [get_ports { led[4] }];
+set_property -dict { PACKAGE_PIN W16   IOSTANDARD LVCMOS25 } [get_ports { led[5] }];
+set_property -dict { PACKAGE_PIN W15   IOSTANDARD LVCMOS25 } [get_ports { led[6] }];
+set_property -dict { PACKAGE_PIN Y13   IOSTANDARD LVCMOS25 } [get_ports { led[7] }];
+
+# Switches
+set_property -dict { PACKAGE_PIN E22  IOSTANDARD LVCMOS12 } [get_ports { sw[0] }];
+set_property -dict { PACKAGE_PIN F21  IOSTANDARD LVCMOS12 } [get_ports { sw[1] }];
+set_property -dict { PACKAGE_PIN G21  IOSTANDARD LVCMOS12 } [get_ports { sw[2] }];
+set_property -dict { PACKAGE_PIN G22  IOSTANDARD LVCMOS12 } [get_ports { sw[3] }];
+set_property -dict { PACKAGE_PIN H17  IOSTANDARD LVCMOS12 } [get_ports { sw[4] }];
+set_property -dict { PACKAGE_PIN J16  IOSTANDARD LVCMOS12 } [get_ports { sw[5] }];
+set_property -dict { PACKAGE_PIN K13  IOSTANDARD LVCMOS12 } [get_ports { sw[6] }];
+set_property -dict { PACKAGE_PIN M17  IOSTANDARD LVCMOS12 } [get_ports { sw[7] }];
+
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property CFGBVS VCCO [current_design]

examples/verilog/nexys_video/uart_host_to_fpga_mem/write.py

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+from manta import Manta
+
+m = Manta("manta.yaml")
+
+# Memory addresses can be written to in Python, and then be read out by
+# flipping the switches on the FPGA, and watching the LEDs update!
+
+m.my_memory.write(0, 1)

examples/verilog/nexys_video/uart_io_core/.gitignore

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+!top_level.sv

examples/verilog/nexys_video/uart_io_core/blinky.py

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+from manta import Manta
+from time import sleep
+from random import randint
+
+m = Manta("manta.yaml")
+
+i = 0
+while True:
+    i = (i + 1) % 8
+    m.my_io_core.set_probe("led", 2**i)
+
+
+    print(f'Switches: {m.my_io_core.get_probe("sw")}')
+    print(f"Buttons:")
+    print(f'btnu: {m.my_io_core.get_probe("btnu")}')
+    print(f'btnd: {m.my_io_core.get_probe("btnd")}')
+    print(f'btnr: {m.my_io_core.get_probe("btnr")}')
+    print(f'btnl: {m.my_io_core.get_probe("btnl")}')
+    print(f'btnc: {m.my_io_core.get_probe("btnc")}')
+    print(f'btnc: {m.my_io_core.get_probe("cpu_resetn")}')
+    print("")
+
+    sleep(0.1)

examples/verilog/nexys_video/uart_io_core/build.sh

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+python3 -m manta gen manta.yaml manta.v
+mkdir -p build/
+$VIVADO -mode batch -source build.tcl

examples/verilog/nexys_video/uart_io_core/build.tcl

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+#!/usr/bin/tclsh
+
+set partNum xc7a200tsbg484-1
+set outputDir build
+
+read_verilog -sv [ glob *.{sv,v,svh,vh} ]
+read_xdc top_level.xdc
+
+set_part $partNum
+
+# synth
+synth_design -top top_level -part $partNum -verbose
+report_utilization -file $outputDir/post_synth_util.rpt
+report_timing_summary -file $outputDir/post_synth_timing_summary.rpt
+report_timing -file $outputDir/post_synth_timing.rpt
+
+# place
+opt_design
+place_design
+phys_opt_design
+report_utilization -file $outputDir/post_place_util.rpt
+
+report_clock_utilization -file $outputDir/clock_util.rpt
+report_timing_summary -file $outputDir/post_place_timing_summary.rpt
+report_timing -file $outputDir/post_place_timing.rpt
+
+# route design and generate bitstream
+route_design -directive Explore
+write_bitstream -force $outputDir/out.bit
+
+report_route_status -file $outputDir/post_route_status.rpt
+report_timing_summary -file $outputDir/post_route_timing_summary.rpt
+report_timing -file $outputDir/post_route_timing.rpt
+report_power -file $outputDir/post_route_power.rpt
+report_drc -file $outputDir/post_imp_drc.rpt
+write_verilog -force $outputDir/cpu_impl_netlist.v -mode timesim -sdf_anno true

examples/verilog/nexys_video/uart_io_core/manta.yaml

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+---
+cores:
+  my_io_core:
+    type: io
+
+    inputs:
+      btnu: 1
+      btnd: 1
+      btnl: 1
+      btnr: 1
+      btnc: 1
+      cpu_resetn: 1
+      sw: 8
+
+    outputs:
+      led: 8
+
+uart:
+  port: "/dev/ttyUSB1"
+  baudrate: 115200
+  clock_freq: 100000000

examples/verilog/nexys_video/uart_io_core/top_level.sv

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+`default_nettype none
+`timescale 1ns / 1ps
+
+module top_level (
+	input wire clk_100mhz,
+
+    input wire uart_tx_in,
+	output logic uart_rx_out,
+
+    input wire btnu,
+    input wire btnd,
+    input wire btnl,
+    input wire btnr,
+	input wire btnc,
+    input wire cpu_resetn,
+
+    input wire [7:0] sw,
+
+	output logic [7:0] led);
+
+    manta manta_inst (
+        .clk(clk_100mhz),
+        .rst(0),
+
+        .rx(uart_tx_in),
+        .tx(uart_rx_out),
+
+        .btnu(btnu),
+        .btnd(btnd),
+        .btnl(btnl),
+        .btnr(btnr),
+        .btnc(btnc),
+        .cpu_resetn(cpu_resetn),
+        .sw(sw),
+        .led(led));
+
+endmodule
+
+`default_nettype wire

examples/verilog/nexys_video/uart_io_core/top_level.xdc

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+# Clock
+set_property -dict { PACKAGE_PIN R4    IOSTANDARD LVCMOS33 } [get_ports { clk_100mhz }];
+create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk_100mhz]
+
+# UART
+set_property -dict { PACKAGE_PIN AA19  IOSTANDARD LVCMOS33 } [get_ports { uart_rx_out }];
+set_property -dict { PACKAGE_PIN V18   IOSTANDARD LVCMOS33 } [get_ports { uart_tx_in }];
+
+# LEDs
+set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS25 } [get_ports { led[0] }];
+set_property -dict { PACKAGE_PIN T15   IOSTANDARD LVCMOS25 } [get_ports { led[1] }];
+set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS25 } [get_ports { led[2] }];
+set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS25 } [get_ports { led[3] }];
+set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS25 } [get_ports { led[4] }];
+set_property -dict { PACKAGE_PIN W16   IOSTANDARD LVCMOS25 } [get_ports { led[5] }];
+set_property -dict { PACKAGE_PIN W15   IOSTANDARD LVCMOS25 } [get_ports { led[6] }];
+set_property -dict { PACKAGE_PIN Y13   IOSTANDARD LVCMOS25 } [get_ports { led[7] }];
+
+# Buttons
+set_property -dict { PACKAGE_PIN B22 IOSTANDARD LVCMOS12 } [get_ports { btnc }];
+set_property -dict { PACKAGE_PIN D22 IOSTANDARD LVCMOS12 } [get_ports { btnd }];
+set_property -dict { PACKAGE_PIN C22 IOSTANDARD LVCMOS12 } [get_ports { btnl }];
+set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS12 } [get_ports { btnr }];
+set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS12 } [get_ports { btnu }];
+set_property -dict { PACKAGE_PIN G4  IOSTANDARD LVCMOS15 } [get_ports { cpu_resetn }];
+
+# Switches
+set_property -dict { PACKAGE_PIN E22  IOSTANDARD LVCMOS12 } [get_ports { sw[0] }];
+set_property -dict { PACKAGE_PIN F21  IOSTANDARD LVCMOS12 } [get_ports { sw[1] }];
+set_property -dict { PACKAGE_PIN G21  IOSTANDARD LVCMOS12 } [get_ports { sw[2] }];
+set_property -dict { PACKAGE_PIN G22  IOSTANDARD LVCMOS12 } [get_ports { sw[3] }];
+set_property -dict { PACKAGE_PIN H17  IOSTANDARD LVCMOS12 } [get_ports { sw[4] }];
+set_property -dict { PACKAGE_PIN J16  IOSTANDARD LVCMOS12 } [get_ports { sw[5] }];
+set_property -dict { PACKAGE_PIN K13  IOSTANDARD LVCMOS12 } [get_ports { sw[6] }];
+set_property -dict { PACKAGE_PIN M17  IOSTANDARD LVCMOS12 } [get_ports { sw[7] }];
+
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property CFGBVS VCCO [current_design]