"csubcircuit" but swaps the first two pins (with the device
identifier layer becoming the 2nd pin and the other terminal the
first), which is needed for n-type diodes modeled as subcircuits
where the subcircuit pin order matches the order of pins for a
SPICE n-type diode component. Previously "msubcircuit" was used
for this purpose, but will calculate the wrong L and W. While
use of L and W for diodes is rare, this device type also works for
reversed capacitors (where the bottom or non-identifying layer
terminal is in the first pin position of the subcircuit).
for a resistor or capacitor is optional but is valid SPICE and not
just limited to CDL format, so it is now allowed to add "r=" at
the end of a resistor or capacitor component (not subcircuit) to
generate the optional component value.
as-is, without a parameter name and before any device model name or
substrate pin, according to CDL syntax, if the parameter has been
specified without a parameter name (e.g., "r=" instead of "r=r").
Corrected an error in the extract code which put the substrate node
name in front of parameters instead of after. This was previously
unexercised because only in CDL format does a resistor or capacitor
model have parameters listed by name.
specified without a list of substrate connection types, but
the "s=" parameter is used, resulting in an attempt to access a
substrate node that does not exist.
1) Corrected spurious error messages about cells already existing
in GDS when using "flatten" or "flatglob".
2) Fixed handling of resistance as a subcircuit parameter
3) Added area and perimeter resistance for a device; this is done
through the "devresist" statement in the tech file, which is an
extension of the original "fetresist" statement. Where "fetresist"
only supported type "linear", "devresist" supports types "area"
and "perimeter".
4) Support for CDL syntax, including generating subcircuit-like
parameters for components starting with SPICE-standard prefixes
like M, R, C, etc., adding "/" between pins and subcircuit name,
and saving the file as ".cdl" instead of ".spice".
5) Estimated L and W for devices whose geometry is complex and do not
reduce to a simple rectangle. L and W are estimated as the square
root of the area.
6) Changed the method of extracting L and W for diodes to use the same
method as capacitors. Note that diodes are not usually specified
by L and W, but if they are, this will produce the right result.
7) Corrected the reported filename and line number when printing error
messages related to errors inside a technology file, when the
technology file uses "include" to combine multiple files.
version 8.3.521 that, due to an argument size mismatch, causes
device parameters in netlist output to be printed as zero.
Also added a small extension to the list of extraction types
to include "device veriloga", which has the same syntax as
"device subcircuit" but generates a component type "N"
(Verilog-A component) in the netlist output.
Additionally the HierName's hierName1 and hierName2 arguments have been
made 'const' to help convey the receiver can not modify the referenced
data passed.
int spcnAP() follows K&R param ordering
int spcnAPHier() follows K&R param ordering
TODO mergeAttr() sharing references (does this setup a future potential
use-after-free concern?)
different from the device (i.e., gate) width, for devices that do
not define a MOS-like gate spanning the width of the device. This
is restricted to the assumption that the terminal is rectangular
and therefore a simple width and length can be derived from the
area and perimeter. Also, length is defined as the smaller
dimension and width as the larger dimension. For additional
restrictions, see the updated documentation. This was added to
allow correct width and length extraction of a bipolar emitter
window, but may be more generally useful.
The '&' has higher precedence, so the expression of the '&' side receive
extra parentheses.
ResMakeRes.c:671:37: warning: suggest parentheses around '&&' within '||'
ResMakeRes.c:942:32: warning: suggest parentheses around '&&' within '||'
ResSimple.c:201:70: warning: suggest parentheses around '&&' within '||'
ResRex.c:1036:28: warning: suggest parentheses around '&&' within '||'
ResRex.c:1038:50: warning: suggest parentheses around '&&' within '||'
ext2sim.c:1341:47: warning: suggest parentheses around '&&' within '||'
ext2spice.c:172:44: warning: suggest parentheses around '&&' within '||'
ext2spice.c:173:49: warning: suggest parentheses around '&&' within '||'
ext2spice.c:3655:50: warning: suggest parentheses around '&&' within '||'
ext2hier.c:1412:50: warning: suggest parentheses around '&&' within '||'
gcrDebug.c:638:55: warning: suggest parentheses around '&&' within '||'
selEnum.c:323:28: warning: suggest parentheses around '&&' within '||'
GCC14 -Wall cleanup series [-Wparentheses]
"extract unique notopports" both fail to work correctly because
an attempt some time ago to avoid issuing warnings about shorted
port names when using those options was changed in the wrong
line.
angled edges. This is a rare case and so has never come up before,
but can happen especially on transistors with gate or diffusion
with 45 degree chamfers or flanges. Thanks to Mark Martin for
providing the use case.
Fix code scanning alert no. 42: Multiplication result converted to larger type (#65)
Co-authored-by: Copilot Autofix powered by AI <62310815+github-advanced-security[bot]@users.noreply.github.com>
Fix code scanning alert no. 40: Multiplication result converted to larger type (#64)
Co-authored-by: Copilot Autofix powered by AI <62310815+github-advanced-security[bot]@users.noreply.github.com>
Fix code scanning alert no. 37: Multiplication result converted to larger type (#58)
Co-authored-by: Copilot Autofix powered by AI <62310815+github-advanced-security[bot]@users.noreply.github.com>
Fix code scanning alert no. 36: Multiplication result converted to larger type (#57)
Co-authored-by: Copilot Autofix powered by AI <62310815+github-advanced-security[bot]@users.noreply.github.com>
'+' and '-' in the same way that '*' is currently used for specifying
a parameter scaling. The combination of a scale and offset for the
same parameter has not (yet) been implemented.
NaN results for devices which are not FETs (specifically, devices
that are declared using "msubckt" but are not FETs, although there
may have been a related issue with non-FET devices not getting the
correct M count), due to the device having zero measured width or
length. NOTE: This may need more investigation. If a subcircuit
device's method of merging cannot be understood, then such devices
should never extract with "merge aggressive", and should always
merge conservatively if and only if all parameters match.
ground node name (which is static) gets put on the node list and
is improperly deallocated. Corrected by simply allocating the
string for the default substrate node instead of using the static
string.
and ext2sim to make use of the new esSIvalue() routine, so that
it no longer depends on a preformatted string. Corrected an
issue where the esSIvalue() routine would output "a" for "atto"
which is not supported by ngspice.
isolate the terminal areas of a device (e.g., source and drain)
and calculate their area and perimeter individually for the
device (in addition to the traditional method of calculating
area and perimeter of each resistance class for the entire node).
Also: Reworked the SPICE syntax output to generate SI values
in the range 1-1000 with the appropriate suffix (e.g., "20u")
instead of defaulting to "u" for lengths and "p" for areas.
This prevents it from producing weird units like "150000u" when
a process definition already includes a scalefactor.
Reworked the "extresist" code to use the device terminal area
and perimeter. This fixes an error in which "extresist" would
lose these values and "ext2spice" with option "extresist on"
would generate a new netlist output with zero terminal areas
and perimeters.
parameters l1 and l2. Provides a way to pass the source or drain
length as a parameter for, for example, an extended FET drain
implemented as a resistor abutting the FET gate. Could potentially
be used as a way to determine source/drain area and perimeter
without resorting to measurements of a shared node.
redundant (same name, different net). Previously, the method was
to keep the first such node and ignore all others except to add
their resistance and capacitance to the original node. This
prevented routines like "def write" from enumerating all nets
unless they had unique names. The new method keeps the additional
records including the node location where they can be found by
EFNodeVisit(), but flags them with EF_UNIQUE_NODE so that routines
like ext2spice or ext2sim can choose to ignore them. This implies
that this method could be used to reimplement "extract unique"
within "ext2spice" or "ext2sim" without altering label text. This
has not yet been implemented.
This commit makes the code (mostly) C99-compatible, enabling to compile
it without the -Wno-error=implicit-function-declaration flag. This
way, Magic becomes usable on arm64 architectures, specifically on Apple
computers with M1/M2 SoC.
prevents magic from crashing but does not do anything about the
fact that a non-existent node ended up in the .ext file, which
will have to be investigated.
which instead of defining a device or subcircuit that exists inside
the cell, instead redefines the cell itself as a device or subcircuit
model that exists in the PDK. This is used where a specific layout
subcell has its own associated device definition in the PDK. Instead
of the "device" property value being the line that gets generated for
a device in the subcells .ext file, the property value should be the
word "primitive" optionally followed by any parameters that need to
be passed to the subcircuit call.
EF_SUBS_PORT flags up the hierarchy. This is a rather lot of code
needed to make substrate connections to circuits where the substrate
connects to devices but not make such connections where the substrate
doesn't. There may be simpler ways to accomplish the same thing,
depending on whether the order of "merge" statements in a .ext file
is reliable; this code does not depend on it.
traditionally been kept for backwards compatibility. However, the
operation of "ext2spice" and "ext2sim" as separate programs has
become extremely difficult to maintain, and so it has been dropped
in favor of folding both into the program as commands, as was done
a long time ago in the Tcl/Tk version.
found to make ext2spice runtimes very long for large layouts.
The new method is equivalent but doesn't incur the overhead.
Also: Changed a flag check which was causing the substrate node
to be output as a port for certain layouts where the substrate
node connects to no devices, and so should be optimized out.
substrate (bulk terminal) and global substrate. Otherwise, the
routine in ext2hier.c that finds the substrate node will find the
first device bulk connection, not the default substrate.
client data generated by ext2spice and attached to a node's
nodeClient record; there is an initNodeClient() routine but no
corresponding freeNodeClient() routine. Eventually had to add a
callback function passed to EFDone() and EFFlatDone() to clean up
these entries. After doing that, valgrind reports clean for all
memory allocated within ext2spice (there are other things that are
not freed but not related to a specific command, so do not need to
be treated as leaks).
this limited ports to 16384, which seemed reasonable at the time.
However, the sky130_sram_macro layouts connect power and ground in a
way that when coupled with "extract unique" can generate tens of
thousands of ports and overrun the bit field, showing that automation
can do the unexpected. The solution was to split out the port number
from the label record as its own 32-bit value.
substrate nodes in subcircuits that don't make connections to the
substrate (such as arrays of pFETs). This is done under the
restriction that ext2spice is being called without generating
parasitics (otherwise the connection to substrate is valid), as it
would be when extracting for LVS. The ground node must not appear
as a connection to any device. This is then propagated up the
hierarchy such that if none of a subcell's descendents connect to
the substrate, then neither does the subcell.
implements a method for handling ports in a subcircuit that have different
port names and indexes but are shorted together. "none" is the default
and backwards-compatible behavior that merges ports together, which will
often cause one of the ports to be optimized out of the netlist. "resistor"
will separate the port names with a 0-ohm ideal resistor. "voltage" will
separate the port names with a 0-volt voltage source. This should work
well for simulation and potentially for LVS, although its impact on LVS
has not been fully investigated.
R. Timothy Edwards
Darryl L. Miles
Alessandro De Laurenzis