Corrected the "bloat-all" function so that it behaves properly on

angled edges.  This is a rare case and so has never come up before,
but can happen especially on transistors with gate or diffusion
with 45 degree chamfers or flanges.  Thanks to Mark Martin for
providing the use case.
This commit is contained in:
Tim Edwards 2024-10-03 20:37:43 -04:00
parent 80f051f79d
commit 6162a9f459
3 changed files with 26 additions and 7 deletions

View File

@ -1 +1 @@
8.3.493
8.3.494

View File

@ -1379,8 +1379,24 @@ cifBloatAllFunc(tile, bls)
area.r_xtop *= locScale;
area.r_ytop *= locScale;
DBNMPaintPlane(cifPlane, TiGetTypeExact(t), &area,
CIFPaintTable, (PaintUndoInfo *) NULL);
/* Diagonal: If expanding across the edge of a diagonal, */
/* then just fill the whole tile. */
if (IsSplit(t))
{
TileType tt;
tt = TiGetTypeExact(t);
if ((tt & TT_SIDE) && (TTMaskHasType(connect, TiGetLeftType(t))))
DBPaintPlane(cifPlane, &area, CIFPaintTable, (PaintUndoInfo *) NULL);
else if (!(tt & TT_SIDE) && (TTMaskHasType(connect, TiGetRightType(t))))
DBPaintPlane(cifPlane, &area, CIFPaintTable, (PaintUndoInfo *) NULL);
else
DBNMPaintPlane(cifPlane, TiGetTypeExact(t), &area,
CIFPaintTable, (PaintUndoInfo *) NULL);
}
else
DBNMPaintPlane(cifPlane, TiGetTypeExact(t), &area,
CIFPaintTable, (PaintUndoInfo *) NULL);
/* Top */
for (tp = RT(t); RIGHT(tp) > LEFT(t); tp = BL(tp))
@ -1401,6 +1417,7 @@ cifBloatAllFunc(tile, bls)
for (tp = TR(t); TOP(tp) > BOTTOM(t); tp = LB(tp))
if (TTMaskHasType(connect, TiGetLeftType(tp)))
PUSHTILE(tp, BloatStack);
}
/* Clear the tiles that were processed */

View File

@ -1874,11 +1874,13 @@ esMakePorts(hc, cdata)
{
nn->efnn_node->efnode_flags |= EF_PORT;
nn->efnn_port = -1; // Will be sorted later
}
// Diagnostic
// TxPrintf("Port connection in %s from net %s to net %s (%s)\n",
// def->def_name, locname, name, portname);
// Diagnostic
/* TxPrintf("Port connection in %s from net %s to "
* "net %s (%s)\n",
* def->def_name, locname, name, portname);
*/
}
}
/* Propagate the EF_SUBS_PORT flag */