Updated the version to go along with the merge of pull request
version 8.3.521 that, due to an argument size mismatch, causes device parameters in netlist output to be printed as zero. Also added a small extension to the list of extraction types to include "device veriloga", which has the same syntax as "device subcircuit" but generates a component type "N" (Verilog-A component) in the netlist output.
This commit is contained in:
R. Timothy Edwards
parent
56598ca0f4
commit
b4912fd550
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@ -1127,6 +1127,13 @@ simdevVisit(
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fprintf(esSimF, "x");
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break;
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case DEV_VERILOGA:
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/* Treat verilog-A models as subcircuits (for now, anyway) */
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/* since IRSIM has no concept of verilog-A models. */
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is_subckt = TRUE;
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fprintf(esSimF, "x");
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break;
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default:
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fprintf(esSimF, "%c", EFDevTypes[dev->dev_type][0]);
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break;
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@ -688,6 +688,9 @@ spcdevHierVisit(
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case DEV_CAPREV:
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devchar = 'C';
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break;
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case DEV_VERILOGA:
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devchar = 'N';
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break;
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case DEV_SUBCKT:
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case DEV_RSUBCKT:
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case DEV_CSUBCKT:
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@ -725,6 +728,7 @@ spcdevHierVisit(
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fprintf(esSpiceF, "%d", esVoltNum++);
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break;
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case DEV_SUBCKT:
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case DEV_VERILOGA:
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case DEV_RSUBCKT:
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case DEV_CSUBCKT:
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case DEV_MSUBCKT:
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@ -778,6 +782,7 @@ spcdevHierVisit(
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/* Drop through to below (no break statement) */
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case DEV_SUBCKT:
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case DEV_VERILOGA:
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case DEV_CSUBCKT:
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/* Subcircuit is "Xnnn gate [source [drain [sub]]]" */
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@ -809,8 +814,8 @@ spcdevHierVisit(
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spcdevOutNode(hc->hc_hierName, source->dterm_node->efnode_name->efnn_hier,
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"subckt", esSpiceF);
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}
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/* The following only applies to DEV_SUBCKT*, which may define as */
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/* many terminal types as it wants. */
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/* The following only applies to DEV_SUBCKT and DEV_VERILOGA, which */
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/* may define as many terminal types as they want. */
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for (i = 4; i < dev->dev_nterm; i++)
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{
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@ -2531,6 +2531,7 @@ spcdevVisit(
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switch(dev->dev_class)
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{
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case DEV_SUBCKT:
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case DEV_VERILOGA:
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case DEV_RSUBCKT:
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case DEV_CSUBCKT:
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case DEV_MSUBCKT:
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@ -2624,6 +2625,9 @@ spcdevVisit(
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case DEV_CAPREV:
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devchar = 'C';
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break;
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case DEV_VERILOGA:
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devchar = 'N';
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break;
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case DEV_SUBCKT:
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case DEV_RSUBCKT:
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case DEV_CSUBCKT:
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@ -2665,6 +2669,7 @@ spcdevVisit(
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fprintf(esSpiceF, "%d", esVoltNum++);
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break;
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case DEV_SUBCKT:
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case DEV_VERILOGA:
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case DEV_RSUBCKT:
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case DEV_CSUBCKT:
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case DEV_MSUBCKT:
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@ -2716,6 +2721,7 @@ spcdevVisit(
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case DEV_SUBCKT:
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case DEV_CSUBCKT:
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case DEV_VERILOGA:
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/* Subcircuit is "Xnnn gate [source [drain [sub]]]" */
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/* Subcircuit .subckt record must be ordered to match! */
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@ -2746,8 +2752,8 @@ spcdevVisit(
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name, esSpiceF);
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}
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/* The following only applies to DEV_SUBCKT*, which may define as */
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/* many terminal types as it wants. */
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/* The following only applies to DEV_SUBCKT and DEV_VERILOGA, which */
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/* may define as many terminal types as they want. */
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for (i = 4; i < dev->dev_nterm; i++)
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{
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@ -4251,6 +4257,7 @@ parallelDevs(
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/* There is no way to merge subcircuit devices */
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case DEV_SUBCKT:
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case DEV_VERILOGA:
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case DEV_RSUBCKT:
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case DEV_CSUBCKT:
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break;
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@ -891,6 +891,7 @@ efBuildDevice(def, class, type, r, argc, argv)
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argstart = 2;
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break;
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case DEV_SUBCKT:
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case DEV_VERILOGA:
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case DEV_MSUBCKT:
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case DEV_RSUBCKT:
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case DEV_CSUBCKT:
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@ -977,6 +978,7 @@ efBuildDevice(def, class, type, r, argc, argv)
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case DEV_CSUBCKT:
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case DEV_MSUBCKT:
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case DEV_SUBCKT:
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case DEV_VERILOGA:
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case DEV_DIODE:
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case DEV_NDIODE:
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case DEV_PDIODE:
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@ -49,7 +49,8 @@ static char rcsid[] __attribute__ ((unused)) = "$Header: /usr/cvsroot/magic-8.0/
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/* This must match the definition for extDevTable in extract/ExtBasic.c */
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const char * const extDevTable[] = {"fet", "mosfet", "asymmetric", "bjt", "devres",
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"devcap", "devcaprev", "vsource", "diode", "pdiode",
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"ndiode", "subckt", "rsubckt", "msubckt", "csubckt", NULL};
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"ndiode", "subckt", "rsubckt", "msubckt", "csubckt",
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"veriloga", NULL};
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#endif
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/*
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@ -368,6 +369,7 @@ readfile:
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ac = 9; /* Has device L and W */
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break;
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case DEV_SUBCKT:
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case DEV_VERILOGA:
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case DEV_MSUBCKT:
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case DEV_RSUBCKT:
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case DEV_CSUBCKT:
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@ -186,6 +186,7 @@ EFGetLengthAndWidth(dev, lptr, wptr)
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case DEV_ASYMMETRIC:
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case DEV_BJT:
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case DEV_SUBCKT:
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case DEV_VERILOGA:
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case DEV_MSUBCKT:
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case DEV_RSUBCKT:
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case DEV_CSUBCKT:
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@ -57,7 +57,7 @@ static char sccsid[] = "@(#)ExtBasic.c 4.13 MAGIC (Berkeley) 12/5/85";
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#ifdef MAGIC_WRAPPER
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const char * const extDevTable[] = {"fet", "mosfet", "asymmetric", "bjt", "devres",
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"devcap", "devcaprev", "vsource", "diode", "pdiode", "ndiode",
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"subckt", "rsubckt", "msubckt", "csubckt", NULL};
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"subckt", "rsubckt", "msubckt", "csubckt", "veriloga", NULL};
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#endif
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/* --------------------- Data local to this file ---------------------- */
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@ -2525,6 +2525,7 @@ extOutputDevices(def, transList, outFile)
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case DEV_MOSFET:
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case DEV_BJT:
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case DEV_SUBCKT:
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case DEV_VERILOGA:
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case DEV_MSUBCKT:
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case DEV_ASYMMETRIC:
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length = 0;
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@ -197,7 +197,7 @@ static const keydesc keyTable[] = {
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* Table used for parsing the "device" keyword types
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*
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* (Note: "10" for max types in subcircuit is arbitrary---the parser
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* ignores max types for DEV_SUBCKT and DEV_MSUBCKT).
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* ignores max types for DEV_SUBCKT, DEV_MSUBCKT, and DEV_VERILOGA).
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*/
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/* types are enumerated in extract.h */
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@ -239,6 +239,9 @@ static const keydesc devTable[] = {
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{"csubcircuit", DEV_CSUBCKT, 4, 7,
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"name dev-types terminal-types [sub-types|None sub-node] [options]"},
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{"veriloga", DEV_VERILOGA, 3, 11,
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"name dev-types [N] [term1-types ... termN-types [sub-types|None sub-node]] [options]"},
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{0}
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};
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@ -2544,13 +2547,14 @@ ExtTechLine(sectionName, argc, argv)
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/* Check the number of arguments after splitting out */
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/* parameter entries. There is no limit on arguments in */
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/* DEV_SUBCKT and DEV_MSUBCKT. */
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/* DEV_SUBCKT, DEV_MSUBCKT, and DEV_VERILOGA. */
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class = dv->k_key;
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switch (class)
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{
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case DEV_SUBCKT:
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case DEV_MSUBCKT:
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case DEV_VERILOGA:
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break;
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default:
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/* If parameters were saved but the */
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@ -2698,6 +2702,7 @@ ExtTechLine(sectionName, argc, argv)
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case DEV_SUBCKT:
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case DEV_MSUBCKT:
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case DEV_VERILOGA:
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// Determine if [substrate, name] optional arguments
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// are present by checking if the last argument
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// parses as a layer list.
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@ -55,6 +55,7 @@ extern int ExtDoWarn; /* Bitmask of above */
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#define DEV_RSUBCKT 12 /* Resistor-like subcircuit. */
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#define DEV_MSUBCKT 13 /* MOSFET-like subcircuit. */
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#define DEV_CSUBCKT 14 /* Capacitor-like subcircuit. */
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#define DEV_VERILOGA 15 /* Verilog-A model ("N" component) */
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/* Device names for .ext file output (new in version 7.2) */
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/* (defined in extract/ExtBasic.c *and* extflat/EFread.c) */
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