isolate the terminal areas of a device (e.g., source and drain)
and calculate their area and perimeter individually for the
device (in addition to the traditional method of calculating
area and perimeter of each resistance class for the entire node).
Also: Reworked the SPICE syntax output to generate SI values
in the range 1-1000 with the appropriate suffix (e.g., "20u")
instead of defaulting to "u" for lengths and "p" for areas.
This prevents it from producing weird units like "150000u" when
a process definition already includes a scalefactor.
Reworked the "extresist" code to use the device terminal area
and perimeter. This fixes an error in which "extresist" would
lose these values and "ext2spice" with option "extresist on"
would generate a new netlist output with zero terminal areas
and perimeters.
parameters l1 and l2. Provides a way to pass the source or drain
length as a parameter for, for example, an extended FET drain
implemented as a resistor abutting the FET gate. Could potentially
be used as a way to determine source/drain area and perimeter
without resorting to measurements of a shared node.
use of a resistor type as a FET extended drain, allowing the
FET drain node to short across to the other side of the resistor
so that the resistor is absorbed into the FET device. Used with
the GF180MCU process to describe the salicide-block ESD FET types.
attempt is made to write an abstract view to GDS. This behavior can
be overridded with the new command option "gds abstract [enable|disable]".
Also: Corrected extraction to allow split tiles to be set as the
reference tile for a node. Previously this was allowed only if the
tile was the first to be searched, but that can cause different tiles to
be marked as the reference depending on where the search starts,
resulting in different names for the same node in .ext files, which is
bad. Also: Modified the LEF annotation to avoid bad entries in the LEF
that would create layers in the layout where none exist.
caused by other code that can move the plane of a device to match
the plane of a port. Solved by retaining the original plane of the
node in the extTransRec structure, and using that to determine the
device plane for purposes of calculating perimeters and not double-
counting contacts.
using the newer methods for nearest-edge searching and fringe area
of effect. Removed a same-net check in a routine that removes
capacitances that are redundant due to hierarchical overlaps; these
redundancies must be checked on shapes within the same net. Corrected
(again) an out-of-clip-bounds check.
which instead of defining a device or subcircuit that exists inside
the cell, instead redefines the cell itself as a device or subcircuit
model that exists in the PDK. This is used where a specific layout
subcell has its own associated device definition in the PDK. Instead
of the "device" property value being the line that gets generated for
a device in the subcells .ext file, the property value should be the
word "primitive" optionally followed by any parameters that need to
be passed to the subcircuit call.
Most of this had to do with the incorrect use of the parent's substrate
name in extHierSubstrate(). After the correction, there still remains
an issue that is caused when a labeled isolated substrate region overlaps
an extraction tile boundary. I believe that this particular error has
existed for some time and is not new, so I am committing these changes.
effectively forcing the substrate type (e.g., "pwell") to be defined
as delineating isolated substrate areas only (e.g., pwell in deep nwell
or isosub a.k.a. subcut). It does so by erasing all of the substrate
type out of a cell prior to extraction before redrawing it in the
isolated areas. This avoids issues caused by pwell drawn in separate
unconnected areas of a cell, as these are removed and the area treated
as the default substrate everywhere. Has worked on all layouts tested
so far.
check for abstract views to determine how to handle the substrate
node. Running tests to check if this has any negative impact on
the extraction of abstract views that do not specify substrate
and well types.
traditionally been kept for backwards compatibility. However, the
operation of "ext2spice" and "ext2sim" as separate programs has
become extremely difficult to maintain, and so it has been dropped
in favor of folding both into the program as commands, as was done
a long time ago in the Tcl/Tk version.
time ago by cleaning up excess usage of "equiv" lines in the .ext
file output. The hierarchical extraction code did not distinguish
between node names which were output and those that were not,
requiring a setting "extract do aliases" to force all node aliases
to be output with "equiv" statements. So hierarchical names
might be any alias, whether output or not, and "merge" and "cap"
lines might contain references to nodes that were not output,
causing them to be disconnected nodes. This fix handles the
"extract no aliases" (default) case by flagging node names that
are redundant and not output, and not creating hierarchical names
with them.
node representing the global substrate on cells that are abstract
views. Corrected a typecasting issue in ext2spice.c that throws
a compiler warning. Added another check for a cell being editable
when painting, which is a case that was not covered by the
previous code change to address the same issue.
value 1 after finding a substrate connecting type shielded (by deep
nwell, in the example) from the substrate, thus preventing the
search from processing any remaining substrate types. Solved by
changing the return value to zero to keep the search going.
this limited ports to 16384, which seemed reasonable at the time.
However, the sky130_sram_macro layouts connect power and ground in a
way that when coupled with "extract unique" can generate tens of
thousands of ports and overrun the bit field, showing that automation
can do the unexpected. The solution was to split out the port number
from the label record as its own 32-bit value.
to eliminate all redundant names resulting from redundant labels.
Changed the behavior of "goto" so that it will find local names with
slashes, which are the result of using "flatten". A hierarchical
search is done first, as before, but on failure to find a subcell
component, the local cell is searched for the verbatim name.
statements in the .ext file output to those that mark a port as
equivalent to the node name used elsewhere in the file. This
limits unnecessary output of "equiv" statements that can bog down
ext2spice and other commands that use the .ext file contents.
(since these are interpreted by IRSIM, the only known program to
parse .sim output)---the "ext2sim alias on" option now just moves
such statements from the ".sim" file to a ".al" file. Corrected the
ResSimMerge() routine to reverse the nodes, so that the devices
belonging to the aliased node are added to the original node, instead
of the other way around. This corrects "missing gate" and "missing SD"
errors that occur due to nodes connected through the substrate.
implements a method for handling ports in a subcircuit that have different
port names and indexes but are shorted together. "none" is the default
and backwards-compatible behavior that merges ports together, which will
often cause one of the ports to be optimized out of the netlist. "resistor"
will separate the port names with a 0-ohm ideal resistor. "voltage" will
separate the port names with a 0-volt voltage source. This should work
well for simulation and potentially for LVS, although its impact on LVS
has not been fully investigated.
extracting substrate regions, due to failure to clean up the tagged
tiles after exiting a search due to finding a substrate type that
was not the global substrate.
statement in a .ext file require that all aliases of a node name be
rehashed after a node merge, or else node loops can occur. Also
prevented statements of the form "equiv A A" from being output in
the .ext file, as they are useless.
restricted to its original intent, which is to replace the long name
formed from the plane short name and the "minfinity" coordinate.
This avoids issues with conflicting substrate names derived from a
real layer such as pwell. Also, the global substrate node name now
returns the variable name without the "$" in front if the variable
has not been set to anything. This avoids potential syntax errors
in the netlist.
one terminal of a device as the substrate, but also specifies
shielding types for the substrate, then the extraction cannot just
assume that a missing terminal is connected to the substrate without
first checking that there are no substrate shielding types under the
device.
with two or more terminals other than the device identifier type
tied together) would fail if there were not a device record
specifically matching a one-S/D-terminal device. This is
inconsistent with past behavior, and so has been fixed.
because the opposite type (pwell) is not directly underneath the
gate, but touches it on the plane below. Because the pwell may
be represented by space tiles on the well plane, it was also
necessary to deal with the space type in the bitmask.
type in the device record, which was not updated at the end of
checking terminals for matching device extraction types. so the
boundary survey might see the wrong device type and generate an
incorrect boundary survey as a result.
support asymmetric FETs and other devices like bipolars that have
three distinct terminals. This does not go as far as it should to
make the array independent of the number of declared terminals of
the device. However, it suffices to make, e.g., parameter "a2=area"
work for a bipolar device, and to generate the right drain and source
areas and perimeters for asymmetric (e.g., extended-drain) devices.
device layer type to describe the extraction for both a regular FET
and an extended-drain device. Note that the current code still
requires that the extended-drain device be declared first, and does
not check for this or attempt to reorder if incorrect.
the extractor was not checking temp_subsname as well as glob_subsname,
and so was failing to apply the substrate name to child cells in
"merge" statements in the extract file, causing the substrate to get
disconnected between parent and child.
optional name field to the "substrate" line in the extract section
of the techfile. This is the default name of the substrate if not
connected to anything labeled. It may use a Tcl variable (preferred).
(2) Added command option "instance orientation [-def]" that returns
the orientation of the named or selected instance. The -def option
returns the orientation using DEF naming convention; otherwise, the
naming used with "getcell" is generated.
generating duplicate devices that may have parts overlaid in
different subcells; this failed to filter the check by plane of
the device, and so if any two devices exist at the same point in
two different planes (e.g., metal resistor and a transistor), one
of them would get eliminated.
Conflicts:
VERSION
database/DBcellsrch.c
database/DBconnect.c
extract/ExtInter.c
lef/Depend
utils/Depend
Updated bplane branch with all changes to master since the bplane branch
was last modified.
like resistors where a tile other than space may border the resistor
device on its non-terminal sides (which is handled correctly, and
should not be considered an error).
to multiple entries per device; the resistor length and width calculating
routine lost a break statement and would go into an infinite loop for
resistors with bends in them.
Tim Edwards
Anton Blanchard
Dan Moore