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48 Commits

Author SHA1 Message Date
Matthias Koefferlein bdf5e3c124 WIP: fake pin debug issue with LVS 
Fake pins: pins that happen because something connects to a cell at an
unexpected position. Such a pin is difficult to find. The solution is
to keep those nets and nur purge them so these nets can be identified
in the layout.

Here: is_floating? will be true only if there are no pins. Hence
nets with pins are not removed. is_passive is introduced for nets -
passive nets are such that don't have elements, but a pin.
Circuits are purged if they only have passive nets.
 2019-09-30 21:58:13 +02:00
Matthias Koefferlein 506cfc1c6f WIP: attempt to retain nets which don't have active elements but pins. This is supposed to simplify debugging in case of fake pins. When removing those nets, the pin is very difficult to find. 2019-09-30 20:58:55 +02:00
Matthias Koefferlein e2cc0c48b1 Provide flat and hierarchical 'trace all nets' feature, added Netlist#flatten. 2019-09-06 23:13:21 +02:00
Matthias Koefferlein b1acfe9587 Tried a better deal with floating pins 
1.) is_floating is now only true if there is no device
    and no subcircuit on a net. This means we only purge
    nets if they are really floating. So far we purged
    nets without pins which lead to the mismatch:

    Before purge:
      Layout:            (net) <--> DEVICE.TERMINAL
      Schematic:           PIN <--> DEVICE.TERMINAL

    After purge:
      Layout:           (null) <--> DEVICE.TERMINAL
      Schematic:           PIN <--> DEVICE.TERMINAL

    (null does not match any net)

2.) circuit pin matching was a bit picky. Only when
    one circuit did not have pins, matching was sloppy.

    In real cases however, circuits may have unconnected
    pins:
    - top level pins without a counterpart (no label)
    - subcircuits pins which are not used

    We catch both cases by refining the match: if a pin
    is not used, it does not need to match against
    any other pin. It's reported as "matching against null"
    though.
 2019-08-29 22:25:59 +02:00
Matthias Koefferlein cef96902ad Boundary for circuits, reverted automatic generation of global pins 
- global pins have been generated for device cells too and lead
  to implicit pins which may not be desired. The original problem
  was how to make abstract circuits comparable. This has to be
  solved differently.
- Circuit boundaries are good for displaying the boxes for
  abstract circuits
 2019-07-09 19:55:48 +02:00
Matthias Koefferlein 5ce8dd2684 WIP: added circuit blankout. 2019-07-06 19:50:20 +02:00
Matthias Koefferlein 7c220c63e1 Functional netlist hierarchy tree. 2019-06-06 01:36:07 +02:00
Matthias Koefferlein 6f689863b6 Fixed MSVC build, fixed unit tests. 2019-05-10 21:09:19 +02:00
Matthias Koefferlein 7f9da5e8de Introduced concept of device class templates 
This concept allows to persist at least the standard
(built-in) device classes into L2N DB files. This way
device classes are persisted.
 2019-04-23 19:44:07 +02:00
Matthias Koefferlein 197d99ab62 Unit test fixed. 2019-04-16 07:10:34 +02:00
Matthias Koefferlein eabf558186 netlist exaction: selective net joining with labels 
Now, a glob pattern can be used to identify the labels
which implicitly join nets. Also, net joining now
only happens on top level.
 2019-04-15 23:24:27 +02:00
Matthias Koefferlein df2bd5e80a Netlist: flatten subcircuits, circuits 2019-04-06 23:36:08 +02:00
Matthias Koefferlein 2d4f23abd1 Updated tests. 2019-03-19 00:08:47 +01:00
Matthias Koefferlein d7eb9162ce WIP: unified to_string/to_parsable_string of db::Netlist, step 1 2019-03-18 19:28:20 +01:00
Matthias Koefferlein e4078ca750 String serialization for netlists. 2019-03-18 02:00:33 +01:00
Matthias Koefferlein 4068478887 Implemented SPICE writer + tests. 2019-01-31 00:07:10 +01:00
Matthias Koefferlein 81bf47688e Renamed device model -> device abstract 2019-01-21 22:37:13 +01:00
Matthias Koefferlein a5e2cf58c3 l2n dump format is leaner (device terminal shapes dropped from nets as they are contained in the device abstracts). Some refactoring. 2019-01-19 23:00:19 +01:00
Matthias Koefferlein 438f50091f WIP: Refined output format for l2n 2019-01-16 00:49:51 +01:00
Matthias Koefferlein 4cb8982ca2 WIP: added concept of device model. 2019-01-15 23:03:25 +01:00
Matthias Koefferlein baf50bd0b1 WIP: refactoring - singularization of classes in separate files. 2019-01-10 23:36:52 +01:00
Matthias Koefferlein d4d7ea8022 Updated copyright. 2019-01-08 01:09:25 +01:00
Matthias Koefferlein c80e335cd6 WIP: global nets integration in cluster builder. 2019-01-07 02:08:59 +01:00
Matthias Koefferlein 64c2548ab8 WIP: first steps towards global nets. 2019-01-06 15:28:40 +01:00
Matthias Koefferlein eb435d5d85 WIP: refactoring - separated pins of net into outgoing and subcircuit. 2019-01-06 12:53:22 +01:00
Matthias Koefferlein f989a85642 WIP: introduced Circuit::is_external_net 2018-12-30 18:44:30 +01:00
Matthias Koefferlein c841b84867 WIP: some minor refactoring. 2018-12-30 13:37:52 +01:00
Matthias Koefferlein 293c6f496e WIP: more query functions for netlist classes (i.e. net by name, device by name etc.), some refactoring, GSI bindings, tests. 2018-12-30 13:00:03 +01:00
Matthias Koefferlein 54adb84e27 WIP: locking of netlist for better performance. 2018-12-29 01:04:48 +01:00
Matthias Koefferlein d57ede441c WIP: netlist topology - children, parents, top-down and bottom-up iteration. 2018-12-29 00:48:28 +01:00
Matthias Koefferlein 2f48479838 WIP: a bit of simplification, renaming of methods, parents for subcircuits, devices. References for circuits pointing to subcircuits. 2018-12-28 22:51:11 +01:00
Matthias Koefferlein 8b2902c31b WIP: introduced expanded net name 2018-12-27 10:43:25 +01:00
Matthias Koefferlein bfae347ffb WIP: renaming sub_circuit->subcircuit for consistency 2018-12-27 02:02:17 +01:00
Matthias Koefferlein f0f620b1cd WIP: added subcircuit IDs for easier referencing. 2018-12-27 01:58:34 +01:00
Matthias Koefferlein 2171b98bd8 WIP: introduced device IDs 2018-12-27 00:59:44 +01:00
Matthias Koefferlein bfc0e24d50 WIP: fixed some compiler warnings. 2018-12-26 00:36:34 +01:00
Matthias Koefferlein 195324295d WIP: tests for new net predicates. 2018-12-25 20:56:08 +01:00
Matthias Koefferlein 4f8416766c WIP: renamed port -> terminal for devices. This is correct technical term. A port is a two-terminal entity. 2018-12-25 20:19:37 +01:00
Matthias Koefferlein d9b0b2f775 WIP: Ability to redefine device combination in Ruby (GenericDeviceClass) 2018-12-24 17:22:59 +01:00
Matthias Koefferlein eb6b043c3b Parameter values of db::Device/db::DeviceClass 2018-12-24 13:39:19 +01:00
Matthias Koefferlein c5222c26e3 Added DevicePortProperty class with tests and GSI binding 2018-12-24 01:31:06 +01:00
Matthias Koefferlein aa5e885215 Added Ruby tests for GSI binding of db::Netlist classes 2018-12-24 00:08:34 +01:00
Matthias Koefferlein 9a9482d7c7 Added netlist editing features. 2018-12-22 23:12:45 +01:00
Matthias Koefferlein e51a3a9ed9 Dual netlist representation (nets attached to pins and ports). 2018-12-22 00:29:44 +01:00
Matthias Koefferlein 654afa3ec2 Upward references for db::Net and db::Circuit. 2018-12-21 22:13:37 +01:00
Matthias Koefferlein 83a38037e5 Added cluster_id property to db::Net 2018-12-21 21:53:48 +01:00
Matthias Koefferlein 80999475f4 Added trans and name attributes to db::SubCircuit 2018-12-21 21:47:27 +01:00
Matthias Koefferlein 4dd17c3cd4 WIP: added tests for dbNetlist classes. 2018-12-20 23:29:01 +01:00