Issue solved: some circuit pins may not have a net - these
need to be ignored.
Requirement: all pins with a net must be mapped.
Detached pins are not present in the mapping table.
A dummy mapping table was introduced to allow dropping
of pins in the second circuit too.
Output of compare should not depend on memory location
anymore and pin mismatch reporting should include all
pins.
- edge pairs are normalized before turning them into polygons.
This makes flat and deep implementation more consistent.
- deep region and flat regions were not cooperating in geo
checks
- unnamed layers are not registered in make_layer - this
does not make sense and will just hold a fake ref
- tests now use GDS to represent texts after transformation
(with orientation, OASIS can't do this)
- texts are more consistently handled in the tests
- test debug output is not written in the same format
than golden data unless special normalization is
requested.
- a non-orientable polygon was converted to orientable in
a text because this can be represented in GDS consistently
- DRC testsuite uses "polygons" instead of "input" to achieve
identical behavior for deep and flat mode with respect to
texts
- dbRegionTests are updated because texts are not allowed
for non-original layers too
Texts are not only kept inside original layers, but
also inside deep layers. This enables using texts
from DRC.
However, texts in deep layers are kept as markers.
Mostly they are converted back to texts, but the
orientation will be lost.
The change eliminates the need to using Iterators
in DRC instead of original layers and use of
label layers in deep mode.
A drawback is the presence of marker shapes in
deep mode (unless polygon layers are created).
Also, text output to RDB is not supported from
deep layers currently.
Area and perimeter computation happens hierarchically
now. Magnified instances are supported.
Sizing is implemented hierarchically.
For anisotropic sizing, orientation variants may be
generated. For both isotropic and anisotropic
magnification variants will be created.
Applies to dbHierProcessor.cc:
The issue was related to std::unordered_set/map which
(as the name says) is not ordered. The output of the
boolean core computation step is currently dependent
on the order (it's single pass), hence the order of
the contexts matters.
Using ordered sets where possible and explicit
sorting might help.
- Changed to const & objects in the Spice writer delegate
to non-const & for Ruby/Python reimplementation (as const/non-const
ambiguity is an issue for Ruby/Python we cannot efficiently
work with const refs)
- Updated test data because the previous implementation wasn't
using refs but rather copies of device and device class
objects.
Reimplementing virtual functions with
"const &" arguments wasn't behaving as
expected because these arguments were
copied.
Now, "const &" for arguments (in virtual
function reimplementation) is not implemented
as a copy.
In addition, now it's possible to declare
results as references always (also if const &).
See gsiTest.cc:1078 for example:
// gsi::arg_make_reference makes the function's return value
// always being taken as a reference
gsi::method<C_P, const CopyDetector &, const CopyDetector &, gsi::arg_make_reference> ("pass_cd_cref_as_ref", &C_P::pass_cd_cref)
Reimplementing virtual functions with
"const &" arguments wasn't behaving as
expected because these arguments were
copied.
Now, "const &" for arguments (in virtual
function reimplementation) is not implemented
as a copy.
In addition, now it's possible to declare
results as references always (also if const &).
See gsiTest.cc:1078 for example:
// gsi::arg_make_reference makes the function's return value
// always being taken as a reference
gsi::method<C_P, const CopyDetector &, const CopyDetector &, gsi::arg_make_reference> ("pass_cd_cref_as_ref", &C_P::pass_cd_cref)
The device handling in the netlist extractor was now
entirely moved to device cells. New options are introduced
for exporting these cells. Tests have been updated.
The cause for the problem was that the layout got updated
while iterating causing the mess within the iterator.
This solution is to lock the layout while an iterator
is present. This happens for various Cell and Shapes
iterator, so it's a major enhancement.
The main entry point is RBA::LayoutToNetlist which is the
GSI binding for the layout to netlist extractor. For a first
impression about the abilities of this extractor see the
Ruby tests in testdata/ruby/dbLayoutToNetlist.rb.
The framework itself consists of many classes, specifically
- RBA::Netlist for the netlist representation
- RBA::DeviceClass and superclasses (e.g. RBA::DeviceClassResistor and
RBA::DeviceClassMOS3Transistor) for the description of devices.
- RBA::DeviceExtractor and superclasses (i.e. RBA::DeviceExtractorMOS3Transistor or
the generic RBA::GenericDeviceExtractor) for the implementation of the
device extraction.
- RBA::Connectivity for the description of inter- and intra-layer connections.
- NetlistProperty is the base class for objects that can
be attached to shapes for annotation
- First property type implemented: net name is a way
to annotate net names
- Splitting of shapes on output of booleans
- A bugfix: error happened when pulling intruders from second-next hier level
- Tests added
- Some TODO comments added
This will include the normal Python tests also
in pymod, hence aligning the test base for pymod
and pya.
This feature requires the pya compatibility module.
With these fixes, unit tests pass with MacOS
(set DYLD_LIBRARY_PATH!)
1.) MacOS takes popen vs. pclose seriously
By using fopen we basically spoil the system and other popen
won't work.
2.) For system integrity, MacOS does not propagate DYLD_LIBRARY_PATH
to child processes such as sh. This has to be done explictly.
3.) Search the klayout binary in the right path (klayout.app/...)
4.) Reset KLAYOUT_HOME for less intervention by installed macros
The comments for LoadLayoutOptions#layer_map, #cif_layer_map
and #dxf_layer_map have been updated to reflect the new status
of these properties (which have been methods). The tests
are updated accordingly (layer_map() -> layer_map).
Rationale:
pya.CplxTrans.angle is computed by doing atan2(m_sin, m_cos), but the algorithm used both in C and python for sin, cos and atan2 are not as precise as IEEE's float.
In python, for example, this happens:
``` python
>>> from math import pi, cos, sin, atan2
>>> atan2(sin(45*pi/180), cos(45*pi/180)) * 180 / pi == 45
False
>>> atan2(sin(45*pi/180), cos(45*pi/180)) * 180 / pi, 45
(44.99999999999999, 45)
```
The text writer was made "normalizing": it will introduce
a certain element order (string sorting). This way, OASIS
files can be compared against golden data without
changes in the order due to different implementation of
hash containers.
Needed to refactor the class hierarchy of the Python classes.
Basically the module specific base class was removed as it does
not provide any benefit. The object layout of the PyObject
specialization was modified such that the payload is attached
to the end. This is compatible with the hidden extensions
which Python adds to normal objects.
* Added unit test for this
* Provided an option for easier debugging such issues:
Setting env var KLAYOUT_VERBOSITY will enable debug levels on Python
modules (and all other binaries). Plugin loading issues can
be debugged by setting KLAYOUT_VERBOSITY=21.
The issue was caused by an internal error in the edge processor.
Effectively the weak attractor scheme was causing this problem.
As the weak attractors are making things worse rather than
better I dropped them.
In theory, the weak attractors render an edge undisturbed by
neighboring intersection points, but in cases or parallel edges
this lead to problems: omitting cut points violates the output
edge configuration warranties the the polygon stitcher fails.
In addition, to maintain the solution for bug #74, the cut point
capture condition was relaxed, so that edge crossing the exact
corner of the snapping rectangle of a point are not considered
captured.