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85 Commits

Author SHA1 Message Date
Matthias Koefferlein 4e54715d64 Merge branch 'wip-lvs' 2021-07-06 23:40:44 +02:00
Matthias Koefferlein 4e0d8d92ef Updated doc, reverted netlist writer to write all parameters - it will only write primary parameters for R, L and C 2021-07-05 22:45:40 +02:00
Matthias Koefferlein 24c34f1d60 Updated test data 2021-07-05 22:29:33 +02:00
Matthias Koefferlein e34fc8967a Some enhancements 
* Device#net_for_terminal with terminal name
* Spice writer now dumps all parameters for resistors and caps (also secondary)
* Enabled Spice writer delegate in LVS (spice_format(...))
* Device class factories for built-in device extractors
 2021-07-05 22:22:13 +02:00
Matthias Koefferlein 1a0b05e663 Updated test data 2021-07-02 23:38:38 +02:00
Matthias Koefferlein 2d2cf11308 Added tests for new features. 2021-06-28 23:08:02 +02:00
Matthias Koefferlein ab70c42c68 Some enhancements for strong matching of nets 
* same_nets! method for strong matching
* same_nets and same_nets! except glob pattern to circuits and nets
* both observe case sensitivity
* helper functions for case sensitivity Netlist#is_case_sensitive?, Netlist#case_sensitive=
* Netlist#nets_by_name to get nets from pattern
 2021-06-28 22:33:46 +02:00
Matthias Koefferlein dae5d3227a Enhanced documentation for blank_circuit, consilidated 'blank_circuit' method provided which can be used anywhere 2021-06-28 19:51:57 +02:00
Matthias Koefferlein 24afd571f0 LVS: can be used anywhere now: tolerance and join_symmetric_nets 2021-06-28 18:56:07 +02:00
Matthias Koefferlein c24c0933bf Bugfix: blackbox mode/abstract pins 
Abstract pins are created when pins are not attached to any or only to passive nets
(passive nets are those without device terminals or subcircuit pins).

1. Such pins were treated swappable. Now named pins will not be treated
   swappable but are mapped by name. This enables blackbox models where
   the pins are labelled and must correspond to schematic pins.
2. A bug was present which lead to incorrect handling of abstract
   nets in net compare.
 2021-06-27 22:56:28 +02:00
Matthias Koefferlein fcb966393a Fixed #806: first, the internal error gone. Second, the implementation of custom comparers is simplified as the 'equals' method does not need to be implemented. 2021-05-26 22:39:28 +02:00
Matthias Koefferlein 94e7f0dbd3 Updated test data, fixed DRC/LVS doc. 2021-05-25 23:30:43 +02:00
Matthias Koefferlein c48be51cb6 Made SPICE netlist elements case insensitive in LVS scripts 2021-03-24 22:11:15 +01:00
Matthias Koefferlein 1495d9521c Tests updated. 2021-03-15 16:51:56 +01:00
Matthias Köfferlein 10eee4d895
Fixed #709. (#714) 2021-01-31 19:21:00 +01:00
Matthias Köfferlein b413cb9d74
Netlist compare: Ambiguity resolution through name matching now default (can be turned off) (#594) 
* WIP: some refactoring

* WIP: some refactoring

* Netlist compare: introducing ambiguity resolution by net names

By default now net names are used for resolving ambiguities.
If net names match, they will be used to associate nets if the
choice is ambiguous. This is usually much faster and more reliable
than trying to resolve ambiguities through topology analysis.

This feature can be disabled using "consider_net_names(false)" in
the LVS script.

* Some refactoring, Jenkinsfile modified for better test coverage
 2020-06-29 20:47:57 +02:00
Matthias Koefferlein 43ceeecf6e Golden test data for Ubuntu 20 and Windows, pipe output stream for Windows. 2020-06-27 09:50:55 +02:00
Matthias Koefferlein 868adbceab Updated golden test data 2020-06-26 23:52:18 +02:00
Matthias Koefferlein b91e2324d0 Netlist compare enhancement 
This enhancement targets towards a better resolution
of ambiguities. The enhancement is to utilize knowledge
about device and subcircuit equivalences to avoid stale
branches of the ambiguity resolution tree.

So far following these branches could lead to a
contradictions which render an ambiguitiy resolution
choice useless.

One effect of this change is enhanced reproducibility
of the matching log because some pointers are not
involved anymore.
 2020-06-26 17:01:03 +02:00
Matthias Köfferlein 3246e0d36f
Fixed #565 (SPICE global nets must not produce pins if not present) (#567) 
* Fixed #565 (SPICE global nets must not produce pins if not present)

* Fixed unit tests.
 2020-05-26 23:47:59 +02:00
Matthias Koefferlein ee53869cbd Connect_implicit test with labels. 2020-05-23 21:21:30 +02:00
Matthias Koefferlein 6f7cca81fb Updated test data 2020-05-23 13:19:52 +02:00
Matthias Koefferlein c682cc85d0 Generalized concept of region, texts etc. into 'shape collections'. Fixed LVS and DRC tests. 2020-05-21 23:59:30 +02:00
Matthias Koefferlein c6b48acc76 Some small enhancements 
LVS: max_branch_complexity was wrong and missing from doc.

Updated test cases so MSVC 2017 builds should pass.

Windows build.bat updated so debug builds can be made.
 2020-03-04 21:48:00 +01:00
Matthias Koefferlein 621cb9edcd Another testdata fix for CentOS 6 2020-02-28 07:12:24 +01:00
Matthias Koefferlein 076206074f Updated tests for CentOS 6 2020-02-27 23:46:02 +01:00
Matthias Koefferlein 02e38a2cd1 Merge branch 'issue-482' into issue-471 2020-02-27 15:49:35 +01:00
Matthias Koefferlein 8b73dffcfe Implementation done. Added tests. 2020-02-27 15:40:06 +01:00
Matthias Koefferlein 76f5e19ed8 Enhanced LVS with 'join_symmetric_nets'. Updated doc. Added test. 2020-02-27 13:35:36 +01:00
Matthias Koefferlein d0e6efa484 Implemented #444 (double-height standard-cell support). 2019-12-17 00:12:36 +01:00
Matthias Koefferlein 3441070908 Merge branch 'issue-448' into dvb 2019-12-15 23:57:42 +01:00
Matthias Koefferlein 3e32ca1ada Updated test data for Windows. 2019-12-15 23:54:17 +01:00
Matthias Koefferlein 12c040aa6c Merge branch 'issue-448' into dvb 2019-12-15 20:51:35 +01:00
Matthias Koefferlein e0be042e67 Test data update for CentOS 6 2019-12-15 20:48:56 +01:00
Matthias Koefferlein b802220ae9 Updated test data 2019-12-15 10:48:11 +01:00
Matthias Koefferlein fccd78a222 Fixed #448 and updated test data 2019-12-15 10:37:51 +01:00
Matthias Koefferlein 06a68b77d2 Updated test data for windows. 2019-12-15 10:17:10 +01:00
Matthias Koefferlein d0fc1edf35 Further updates of test data. 2019-12-15 01:45:15 +01:00
Matthias Koefferlein 782f6fe601 BUGFIX: the L2N and LVSDB writer was writing too much 
Sometimes, shapes from child cells were propagated into
parent cells in the L2N and LVSDB output.

Because of this fix, many testdata files have to be updated.
 2019-12-15 01:29:56 +01:00
Matthias Koefferlein ccb1871fb3 Updates for 'cheats' testcase which was entirely broken. 2019-11-23 19:24:59 +01:00
Matthias Koefferlein d5506a176a WIP: first implementation - needs testing. 2019-11-23 01:20:22 +01:00
Matthias Koefferlein ab4f632527 Another unit test golden data set for MinGW32 2019-11-12 20:17:27 +01:00
Matthias Koefferlein 3dffe91f88 Attempt to fix testdata for MSVC 2019-11-03 02:30:52 +01:00
Matthias Koefferlein 7910ddc6a3 Fixed a compiler warning, testcase update (part 1) 2019-11-02 20:39:59 +01:00
Matthias Koefferlein e25d4784ea Updated tests. 2019-10-26 01:48:50 +02:00
Matthias Koefferlein bf18000877 Added tests (breakout cells, LVS cheats) 2019-10-18 00:25:51 +02:00
Matthias Koefferlein ca747771ac Allow preempt LVS configuration 
same_nets, equivalent_pins, same_circuits and same_device_classes
can now be given at the beginning of the LVS script. This will
simplify building universal scripts with the run specific part at
the beginning (one "load" section).

The price are somewhat less specific error messages when something
fails in these methods.
 2019-10-01 00:21:27 +02:00
Matthias Koefferlein a3cecb2ebe WIP: enable multiple layout versions of one schematic circuit using 'same_circuit' 2019-09-30 23:08:15 +02:00
Matthias Koefferlein 55475e905f Fixed #352 (LVS should ignore equivalent_pins line for non-existing circuits) 
Same is true now for same_nets and same_circuits.
 2019-09-15 00:18:29 +02:00
Matthias Koefferlein ab66186db4 Updated MSVC test golden data 2019-08-30 13:03:37 +02:00