mirror of https://github.com/KLayout/klayout.git
Connect_implicit test with labels.
This commit is contained in:
Matthias Koefferlein
parent
f410c91339
commit
ee53869cbd
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@ -182,7 +182,13 @@ TEST(20_double_height2_inv)
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run_test (_this, "double_height2", "double_height2_inv.gds");
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}
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TEST(21_split_gate)
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// testing cell specific net joining for VSS of the double-height inverter standard cell
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TEST(21_double_height2_inv_texts)
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{
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run_test (_this, "double_height2_texts", "double_height2_inv.gds");
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}
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TEST(22_split_gate)
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{
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run_test (_this, "nand2_split_gate", "nand2_split_gate.oas");
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}
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@ -0,0 +1,17 @@
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* Extracted by KLayout
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.SUBCKT INVCHAIN ANY R ANY$1 PWR GND
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X$1 ANY R R ANY$1 PWR GND INV2
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.ENDS INVCHAIN
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.SUBCKT INV2 A1 A2 Q1 Q2 R VSS
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X$1 VSS R A1 Q1 INV
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X$2 VSS R A2 Q2 INV
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.ENDS INV2
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.SUBCKT INV \$1 \$2 \$3 \$4
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M$1 \$4 \$3 \$2 \$4 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
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+ PD=3.45U
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M$2 \$4 \$3 \$1 \$4 NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
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+ PD=3.45U
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.ENDS INV
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@ -0,0 +1,135 @@
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source($lvs_test_source)
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report_lvs($lvs_test_target_lvsdb)
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writer = write_spice(true, false)
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target_netlist($lvs_test_target_cir, writer, "Extracted by KLayout")
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# needs this delegate because we use MOS3 which is not available in Spice
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class SpiceReaderDelegate < RBA::NetlistSpiceReaderDelegate
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# says we want to catch these subcircuits as devices
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def wants_subcircuit(name)
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name == "HVNMOS" || name == "HVPMOS"
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end
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# translate the element
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def element(circuit, el, name, model, value, nets, params)
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if el != "M"
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# all other elements are left to the standard implementation
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return super
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end
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if nets.size != 4
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error("Device #{model} needs four nodes")
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end
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# provide a device class
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cls = circuit.netlist.device_class_by_name(model)
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if ! cls
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cls = RBA::DeviceClassMOS3Transistor::new
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cls.name = model
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circuit.netlist.add(cls)
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end
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# create a device
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device = circuit.create_device(cls, name)
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# and configure the device
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[ "S", "G", "D" ].each_with_index do |t,index|
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device.connect_terminal(t, nets[index])
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end
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device.set_parameter("W", params["W"] * 1e6)
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device.set_parameter("L", params["L"] * 1e6)
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device
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end
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end
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reader = RBA::NetlistSpiceReader::new(SpiceReaderDelegate::new)
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schematic("double_height_inv.cir", reader)
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deep
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# Drawing layers
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nwell = input(1, 0)
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active = input(2, 0)
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poly = input(3, 0)
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poly_lbl = labels(3, 1)
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diff_cont = input(4, 0)
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poly_cont = input(5, 0)
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metal1 = input(6, 0)
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metal1_lbl = labels(6, 1)
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via1 = input(7, 0)
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metal2 = input(8, 0)
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metal2_lbl = labels(8, 1)
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# Bulk layer for terminal provisioning
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bulk = polygon_layer
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psd = nil
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nsd = nil
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# Computed layers
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active_in_nwell = active & nwell
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pactive = active_in_nwell
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pgate = pactive & poly
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psd = pactive - pgate
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active_outside_nwell = active - nwell
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nactive = active_outside_nwell
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ngate = nactive & poly
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nsd = nactive - ngate
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# Device extraction
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# PMOS transistor device extraction
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extract_devices(mos3("PMOS"), { "SD" => psd, "G" => pgate,
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"tS" => psd, "tD" => psd, "tG" => poly })
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# NMOS transistor device extraction
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extract_devices(mos3("NMOS"), { "SD" => nsd, "G" => ngate,
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"tS" => nsd, "tD" => nsd, "tG" => poly })
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# Define connectivity for netlist extraction
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# Inter-layer
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connect(psd, diff_cont)
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connect(nsd, diff_cont)
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connect(poly, poly_cont)
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connect(diff_cont, metal1)
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connect(poly_cont, metal1)
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connect(metal1, via1)
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connect(via1, metal2)
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# attach labels
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connect(poly, poly_lbl)
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connect(metal1, metal1_lbl)
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connect(metal2, metal2_lbl)
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# Global
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connect_global(bulk, "SUBSTRATE")
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# Implicit connection of the INV2
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# VSS nets
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connect_implicit("GND")
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connect_implicit("?") # "R"
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connect_implicit("DOESNOTEXIST")
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connect_implicit("*2", "*SS")
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connect_implicit("*", "R")
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connect_implicit("DOESNOTEXIST", "DOESNOTEXIST")
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# Compare section
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netlist.simplify
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align
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compare
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@ -0,0 +1,325 @@
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#%lvsdb-klayout
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J(
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W(INVCHAIN)
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U(0.001)
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L(l3 '3/0')
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L(l11 '3/1')
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L(l6 '4/0')
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L(l7 '2/0')
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L(l8 '6/0')
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L(l12 '6/1')
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L(l9 '7/0')
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L(l10 '8/0')
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L(l13 '8/1')
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L(l14)
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L(l2)
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L(l5)
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C(l3 l3 l11 l7)
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C(l11 l3)
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C(l6 l6 l8 l2 l5)
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C(l7 l3 l7 l8)
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C(l8 l6 l7 l8 l12 l9)
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C(l12 l8)
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C(l9 l8 l9 l10)
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C(l10 l9 l10 l13)
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C(l13 l10)
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C(l14 l14)
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C(l2 l6 l2)
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C(l5 l6 l5)
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G(l14 SUBSTRATE)
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K(PMOS MOS3)
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K(NMOS MOS3)
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D(D$PMOS PMOS
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T(S
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R(l2 (-900 -475) (775 950))
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)
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T(G
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R(l3 (-125 -475) (250 950))
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)
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T(D
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R(l2 (125 -475) (775 950))
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)
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)
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D(D$NMOS NMOS
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T(S
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R(l5 (-900 -475) (775 950))
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)
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T(G
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R(l3 (-125 -475) (250 950))
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)
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T(D
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R(l5 (125 -475) (775 950))
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)
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)
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X(INV
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R((-1500 -800) (3000 4600))
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N(1
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R(l6 (290 -310) (220 220))
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R(l6 (-220 180) (220 220))
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R(l8 (-290 -690) (360 760))
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R(l9 (-305 -705) (250 250))
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R(l9 (-250 150) (250 250))
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R(l10 (-2025 -775) (3000 900))
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R(l5 (-1375 -925) (775 950))
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)
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N(2
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R(l6 (290 2490) (220 220))
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R(l6 (-220 180) (220 220))
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R(l8 (-290 -690) (360 760))
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R(l9 (-305 -705) (250 250))
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R(l9 (-250 150) (250 250))
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R(l10 (-2025 -775) (3000 900))
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R(l2 (-1375 -925) (775 950))
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)
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N(3
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R(l3 (-125 -250) (250 2500))
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R(l3 (-250 -3050) (250 1600))
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R(l3 (-250 1200) (250 1600))
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)
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N(4
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R(l6 (-510 -310) (220 220))
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R(l6 (-220 180) (220 220))
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R(l6 (-220 2180) (220 220))
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R(l6 (-220 180) (220 220))
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R(l8 (-290 -3530) (360 2840))
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R(l8 (-360 -2800) (360 760))
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R(l8 (-360 2040) (360 760))
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R(l2 (-680 -855) (775 950))
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R(l5 (-775 -3750) (775 950))
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)
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P(1)
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P(2)
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P(3)
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P(4)
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D(1 D$PMOS
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Y(0 2800)
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E(L 0.25)
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E(W 0.95)
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E(AS 0.73625)
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E(AD 0.73625)
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E(PS 3.45)
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E(PD 3.45)
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T(S 4)
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T(G 3)
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T(D 2)
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)
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D(2 D$NMOS
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Y(0 0)
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E(L 0.25)
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E(W 0.95)
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E(AS 0.73625)
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E(AD 0.73625)
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E(PS 3.45)
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E(PD 3.45)
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T(S 4)
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T(G 3)
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T(D 1)
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)
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)
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X(INV2
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R((0 0) (3000 9200))
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N(1 I(A1)
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J(l11 A1 (1480 7110))
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)
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N(2 I(A2)
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J(l11 A2 (1520 1950))
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)
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N(3 I(Q1)
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J(l12 Q1 (1920 7070))
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)
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N(4 I(Q2)
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J(l12 Q2 (1940 1950))
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)
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N(5 I(R)
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J(l13 R (2720 5560))
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J(l13 R (-90 -1940))
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)
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N(6 I(VSS)
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J(l13 VSS (2680 8390))
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J(l13 VSS (-30 -7640))
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)
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P(1 I(A1))
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P(2 I(A2))
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P(3 I(Q1))
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P(4 I(Q2))
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P(5 I(R))
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P(6 I(VSS))
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X(1 INV O(180) Y(1500 8400)
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P(0 6)
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P(1 5)
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P(2 1)
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P(3 3)
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)
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X(2 INV M O(180) Y(1500 800)
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P(0 6)
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P(1 5)
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P(2 2)
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P(3 4)
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)
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)
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X(INVCHAIN
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R((-90 0) (3090 9200))
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N(1 I(ANY)
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R(l3 (-90 6850) (1590 650))
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J(l11 ANY (-700 -350))
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)
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N(2 I(R)
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J(l11 R (1480 2370))
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R(l8 (440 4580) (690 510))
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J(l12 R (-300 -290))
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)
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N(3 I(ANY)
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R(l8 (-90 1720) (1890 470))
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J(l12 ANY (-1170 -230))
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)
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N(4 I(PWR)
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J(l13 PWR (300 5550))
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J(l13 PWR (-10 -1990))
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)
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N(5 I(GND)
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J(l13 GND (320 8400))
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J(l13 GND (-50 -7600))
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)
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P(1 I(ANY))
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P(2 I(R))
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P(3 I(ANY))
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P(4 I(PWR))
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P(5 I(GND))
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X(1 INV2 Y(0 0)
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P(0 1)
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P(1 2)
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P(2 2)
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P(3 3)
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P(4 4)
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P(5 5)
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)
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)
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)
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H(
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K(PMOS MOS3)
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K(NMOS MOS3)
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X(INV
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N(1 I(VDD))
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N(2 I(VSS))
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N(3 I(A))
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N(4 I(Q))
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P(1 I(VDD))
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P(2 I(VSS))
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P(3 I(A))
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P(4 I(Q))
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D(1 PMOS
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I($1)
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E(L 0.25)
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E(W 0.95)
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E(AS 0)
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E(AD 0)
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E(PS 0)
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E(PD 0)
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T(S 1)
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T(G 3)
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T(D 4)
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)
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D(2 NMOS
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I($3)
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E(L 0.25)
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E(W 0.95)
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E(AS 0)
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E(AD 0)
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E(PS 0)
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E(PD 0)
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T(S 2)
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T(G 3)
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T(D 4)
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)
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)
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X(INV2
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N(1 I(VDD))
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N(2 I(VSS))
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N(3 I(A1))
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N(4 I(Q1))
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N(5 I(A2))
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N(6 I(Q2))
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P(1 I(VDD))
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P(2 I(VSS))
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P(3 I(A1))
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P(4 I(Q1))
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P(5 I(A2))
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P(6 I(Q2))
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X(1 INV I($1)
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P(0 1)
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P(1 2)
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P(2 3)
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P(3 4)
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)
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X(2 INV I($2)
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P(0 1)
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P(1 2)
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P(2 5)
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P(3 6)
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)
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)
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X(INVCHAIN
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N(1 I('1'))
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N(2 I('2'))
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N(3 I('3'))
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N(4 I('4'))
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N(5 I('5'))
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X(1 INV2 I($2)
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P(0 1)
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P(1 2)
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P(2 3)
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P(3 4)
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P(4 4)
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P(5 5)
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)
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)
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)
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Z(
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X(INV INV 1
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Z(
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N(3 3 1)
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N(4 4 1)
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N(2 1 1)
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N(1 2 1)
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P(2 2 1)
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P(3 3 1)
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P(1 0 1)
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P(0 1 1)
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D(2 2 1)
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D(1 1 1)
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)
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)
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X(INV2 INV2 1
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Z(
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N(1 3 1)
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N(2 5 1)
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N(3 4 W)
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N(4 6 W)
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N(5 1 1)
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N(6 2 1)
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P(0 2 1)
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P(1 4 1)
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P(2 3 1)
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P(3 5 1)
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P(4 0 1)
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P(5 1 1)
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X(1 1 1)
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X(2 2 1)
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)
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)
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X(INVCHAIN INVCHAIN 1
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Z(
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N(1 3 1)
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N(3 5 1)
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N(5 2 1)
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N(4 1 1)
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N(2 4 1)
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P(2 () 1)
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P(0 () 1)
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P(4 () 1)
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P(3 () 1)
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P(1 () 1)
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X(1 1 1)
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)
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)
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)
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