mirror of https://github.com/KLayout/klayout.git
Enhanced documentation for blank_circuit, consilidated 'blank_circuit' method provided which can be used anywhere
This commit is contained in:
Matthias Koefferlein
parent
e0ccb4f980
commit
dae5d3227a
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@ -3334,7 +3334,7 @@ The tile size must be specified with the "tile_size" option:
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</p><p>
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<pre>
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# reports areas where layer 1/0 density is below 10% on 20x20 um tiles
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low_density = input(1, 0).density(0.0 .. 0.1, tile_size(20.um))
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low_density = input(1, 0).with_density(0.0 .. 0.1, tile_size(20.um))
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</pre>
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</p><p>
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Anisotropic tiles can be specified by giving two values, like "tile_size(10.um, 20.um)".
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@ -3348,7 +3348,7 @@ in increments of the tile step:
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<pre>
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# reports areas where layer 1/0 density is below 10% on 30x30 um tiles
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# with a tile step of 20x20 um:
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low_density = input(1, 0).density(0.0 .. 0.1, tile_size(30.um), tile_step(20.um))
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low_density = input(1, 0).with_density(0.0 .. 0.1, tile_size(30.um), tile_step(20.um))
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</pre>
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</p><p>
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For "tile_step", anisotropic values can be given as well by using two values: the first for the
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@ -3366,7 +3366,7 @@ drawn boundary layer. To specify a separate, additional layer included in the bo
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# reports density of layer 1/0 below 10% on 20x20 um tiles. The layout's boundary is taken from
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# layer 0/0:
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cell_frame = input(0, 0)
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low_density = input(1, 0).density(0.0 .. 0.1, tile_size(20.um), tile_boundary(cell_frame))
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low_density = input(1, 0).with_density(0.0 .. 0.1, tile_size(20.um), tile_boundary(cell_frame))
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</pre>
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</p><p>
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Note that the layer given in "tile_boundary" adds to the input layer for computing the bounding box.
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@ -3378,7 +3378,7 @@ direction. With the "tile_origin" option this allows full control over the area
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<pre>
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# reports density of layer 1/0 below 10% on 20x20 um tiles in the region 0,0 .. 2000,3000
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# (100 and 150 tiles of 20 um each are used in horizontal and vertical direction):
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low_density = input(1, 0).density(0.0 .. 0.1, tile_size(20.um), tile_origin(0.0, 0.0), tile_count(100, 150))
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low_density = input(1, 0).with_density(0.0 .. 0.1, tile_size(20.um), tile_origin(0.0, 0.0), tile_count(100, 150))
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</pre>
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</p><p>
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The "padding mode" indicates how the area outside the layout's bounding box is considered.
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@ -3392,7 +3392,7 @@ There are two modes:
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Example:
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</p><p>
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<pre>
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low_density = input(1, 0).density(0.0 .. 0.1, tile_size(20.um), padding_ignore)
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low_density = input(1, 0).with_density(0.0 .. 0.1, tile_size(20.um), padding_ignore)
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</pre>
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</p><p>
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The complementary version of "with_density" is <a href="#without_density">without_density</a>.
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@ -28,6 +28,15 @@ For more details about the DRC functions see <a href="/about/drc_ref_global.xml"
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<p>
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See <a href="/about/lvs_ref_netter.xml#align">Netter#align</a> for a description of that function.
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</p>
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<a name="blank_circuit"/><h2>"blank_circuit" - Removes the content from the given circuits (blackboxing)</h2>
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<keyword name="blank_circuit"/>
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<p>Usage:</p>
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<ul>
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<li><tt>blank_circuit(circuit_filter)</tt></li>
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</ul>
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<p>
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See <a href="/about/lvs_ref_netter.xml#blank_circuit">Netter#blank_circuit</a> for a description of that function.
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</p>
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<a name="compare"/><h2>"compare" - Compares the extracted netlist vs. the schematic</h2>
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<keyword name="compare"/>
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<p>Usage:</p>
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@ -68,6 +68,34 @@ are other (explicit) ways to flatten circuits.
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Please note that flattening circuits has some side effects such
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as loss of details in the cross reference and net layout.
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</p>
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<a name="blank_circuit"/><h2>"blank_circuit" - Removes the content from the given circuits (blackboxing)</h2>
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<keyword name="blank_circuit"/>
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<p>Usage:</p>
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<ul>
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<li><tt>blank_circuit(circuit_filter)</tt></li>
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</ul>
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<p>
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This method will erase all content from the circuits matching the filter.
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The filter is a glob expression.
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</p><p>
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This has the following effects:
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</p><p>
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<ul>
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<li>The circuits are no longer compared against each other </li>
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<li>Named pins are required to match (use labels on the nets to name pins in the layout) </li>
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<li>Unnamed pins are treated as equivalent and can be swapped </li>
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<li>The selected circuits will not be purged on netlist simplification </li>
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</ul>
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</p><p>
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Using this method can be useful to reduce the verification overhead for
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blocks which are already verifified by other ways or for which no schematic
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is available - e.g. hard macros.
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</p><p>
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<pre>
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# skips all MEMORY* circuits from compare
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blank_circuit("MEMORY*")
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</pre>
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</p>
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<a name="compare"/><h2>"compare" - Compares the extracted netlist vs. the schematic</h2>
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<keyword name="compare"/>
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<p>Usage:</p>
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@ -153,10 +153,11 @@
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<p>
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A useful method in this context is the "blank_circuit" method. It clears
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a circuit's innards and leaves only the pins. You can use this method to
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ensure abstracts in both the layout netlist and the schematic. After this,
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a circuit's innards from a netlist. After this,
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the compare algorithm will identify both circuits as identical, provided
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they feature the same number of pins.
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they feature the same number of pins. Named pins are required to match exactly
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unless declared equivalent. Unnamed pins are treated as equivalent. To name
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pins use labels on the pin's nets inside the circuit's layout.
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</p>
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<p>
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@ -166,14 +167,20 @@
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<pre>netlist.blank_circuit("CIRCUIT_NAME")
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schematic.blank_circuit("CIRCUIT_NAME")</pre>
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<p><b>NOTE:</b> In this version, use "blank_circuit" before "purge" or "simplify" (see below). "blank_circuit"
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sets a flag (<class_doc href="Circuit#dont_purge"/>) which prevents purging of abstract circuits.</p>
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<p>
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The argument to "blank_circuit" is a glob pattern (shell-like).
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For example, "MEMORY*" will blank out all circuits starting with "MEMORY".
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There is a short form for this too (<a href="/about/lvs_ref_netter.xml#blank_circuit">blank_circuit</a>).
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In contrast to netlist-based "blank_circuit", this method can be used anywhere in the LVS script:
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</p>
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<p><b>NOTE:</b> Use "blank_circuit" before "purge" or "simplify" (see below). This method
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sets a flag (<class_doc href="Circuit#dont_purge"/>) which prevents purging of abstract
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circuits.</p>
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<pre>blank_circuit("CIRCUIT_NAME")</pre>
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<p>
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The argument to "blank_circuit" in both cases is a glob pattern (shell-like).
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For example, "MEMORY*" will blank out all circuits starting with the word "MEMORY".
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</p>
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<h2>Joining of symmetric nodes</h2>
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@ -201,8 +208,8 @@ schematic.blank_circuit("CIRCUIT_NAME")</pre>
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</p>
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<p>
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KLayout provides a feature which will add such connections after extraction
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of the netlist:
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KLayout provides a feature (<a href="/about/lvs_ref_netter.xml#join_symmetric_nets">join_symmetric_nets</a>)
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which will add such connections after extraction of the netlist:
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</p>
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<pre>join_symmetric_nets("NAND2")</pre>
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@ -221,6 +228,10 @@ schematic.blank_circuit("CIRCUIT_NAME")</pre>
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need it.
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</p>
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<p>
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"join_symmetric_nets" can be used anywhere in the LVS script.
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</p>
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<h2>Purging (elimination of redundancy)</h2>
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<p>
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@ -100,6 +100,12 @@ module LVS
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# @synopsis join_symmetric_nets(circuit_filter)
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# See \Netter#join_symmetric_nets for a description of that function.
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# %LVS%
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# @name blank_circuit
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# @brief Removes the content from the given circuits (blackboxing)
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# @synopsis blank_circuit(circuit_filter)
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# See \Netter#blank_circuit for a description of that function.
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# %LVS%
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# @name align
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# @brief Aligns the extracted netlist vs. the schematic by flattening circuits where required
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@ -168,7 +174,7 @@ module LVS
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# @synopsis tolerance(device_class_name, parameter_name [, :absolute => absolute_tolerance] [, :relative => relative_tolerance])
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# See \Netter#tolerance for a description of that function.
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%w(schematic compare join_symmetric_nets tolerance align same_nets same_circuits same_device_classes equivalent_pins min_caps max_res max_depth max_branch_complexity consider_net_names).each do |f|
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%w(schematic compare join_symmetric_nets tolerance blank_circuit align same_nets same_circuits same_device_classes equivalent_pins min_caps max_res max_depth max_branch_complexity consider_net_names).each do |f|
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eval <<"CODE"
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def #{f}(*args)
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_netter.#{f}(*args)
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@ -283,6 +283,55 @@ module LVS
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end
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# %LVS%
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# @name blank_circuit
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# @brief Removes the content from the given circuits (blackboxing)
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# @synopsis blank_circuit(circuit_filter)
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# This method will erase all content from the circuits matching the filter.
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# The filter is a glob expression.
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#
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# This has the following effects:
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#
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# @ul
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# @li The circuits are no longer compared (netlist vs. schematic) @/li
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# @li Named pins are required to match (use labels on the nets to name pins in the layout) @/li
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# @li Unnamed pins are treated as equivalent and can be swapped @/li
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# @li The selected circuits will not be purged on netlist simplification @/li
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# @/ul
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#
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# Using this method can be useful to reduce the verification overhead for
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# blocks which are already verifified by other ways or for which no schematic
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# is available - e.g. hard macros.
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#
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# Example:
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#
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# @code
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# # skips all MEMORY* circuits from compare
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# blank_circuit("MEMORY*")
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# @/code
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def blank_circuit(circuit_pattern)
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circuit_pattern.is_a?(String) || raise("Circuit pattern argument of 'blank_circuit' must be a string")
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if self._l2n_data
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# already extracted
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self._blank_circuit(self._l2n_data, circuit_pattern)
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else
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@post_extract_config << lambda { |l2n| self._blank_circuit(l2n, circuit_pattern) }
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end
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end
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def _blank_circuit(l2n, circuit_pattern)
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(n, s) = _ensure_two_netlists
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n.blank_circuit(circuit_pattern)
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s.blank_circuit(circuit_pattern)
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end
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def _comparer
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comparer = RBA::NetlistComparer::new
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@ -135,6 +135,11 @@ TEST(9_blackboxing)
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run_test (_this, "ringo_simple_blackboxing", "ringo_for_blackboxing.gds");
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}
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TEST(9b_blackboxing_netter)
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{
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run_test (_this, "ringo_simple_blackboxing_netter", "ringo_for_blackboxing.gds");
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}
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TEST(10_simplification_with_align)
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{
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run_test (_this, "ringo_simple_simplification_with_align", "ringo_for_simplification.gds");
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@ -0,0 +1,70 @@
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* Extracted by KLayout
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* cell RINGO
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* pin FB
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* pin VDD
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* pin OUT
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* pin ENABLE
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* pin VSS
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.SUBCKT RINGO 5 6 7 8 9
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* net 5 FB
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* net 6 VDD
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* net 7 OUT
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* net 8 ENABLE
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* net 9 VSS
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* cell instance $1 r0 *1 1.8,0
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X$1 6 1 9 6 5 8 9 ND2X1
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* cell instance $2 r0 *1 4.2,0
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X$2 6 2 9 6 1 9 INVX1
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* cell instance $3 r0 *1 6,0
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X$3 6 10 9 6 2 9 INVX1
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* cell instance $4 r0 *1 16.8,0
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X$4 6 3 9 6 11 9 INVX1
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* cell instance $5 r0 *1 18.6,0
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X$5 6 4 9 6 3 9 INVX1
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* cell instance $6 r0 *1 20.4,0
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X$6 6 5 9 6 4 9 INVX1
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* cell instance $7 r0 *1 22.2,0
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X$7 5 6 7 9 6 9 INVX2
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* cell instance $17 r0 *1 7.8,0
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X$17 6 12 9 6 10 9 INVX1
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* cell instance $18 r0 *1 9.6,0
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X$18 6 13 9 6 12 9 INVX1
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* cell instance $19 r0 *1 11.4,0
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X$19 6 14 9 6 13 9 INVX1
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* cell instance $20 r0 *1 13.2,0
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X$20 6 15 9 6 14 9 INVX1
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* cell instance $21 r0 *1 15,0
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X$21 6 11 9 6 15 9 INVX1
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.ENDS RINGO
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* cell INVX2
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* pin IN
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* pin VDD
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* pin OUT
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* pin VSS
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* pin
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* pin BULK
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.SUBCKT INVX2 1 2 3 4 5 6
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.ENDS INVX2
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* cell INVX1
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* pin VDD
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* pin OUT
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* pin VSS
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* pin
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* pin IN
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* pin BULK
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.SUBCKT INVX1 1 2 3 4 5 6
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.ENDS INVX1
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* cell ND2X1
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* pin VDD
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* pin OUT
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* pin VSS
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* pin
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* pin B
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* pin A
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* pin BULK
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.SUBCKT ND2X1 1 2 3 4 5 6 7
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.ENDS ND2X1
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@ -0,0 +1,87 @@
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source($lvs_test_source, "RINGO")
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report_lvs($lvs_test_target_lvsdb, true)
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target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
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schematic("ringo_for_blackboxing.cir")
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blank_circuit("INVX1")
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blank_circuit("INVX2")
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blank_circuit("ND2X1")
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deep
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# Drawing layers
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nwell = input(1, 0)
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active = input(2, 0)
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pplus = input(3, 0)
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nplus = input(4, 0)
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poly = input(5, 0)
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contact = input(8, 0)
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metal1 = input(9, 0)
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via1 = input(10, 0)
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metal2 = input(11, 0)
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# Bulk layer for terminal provisioning
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# and to provide the BULK labels for
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# the abstracts
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bulk = labels(13, 0)
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# Computed layers
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active_in_nwell = active & nwell
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pactive = active_in_nwell & pplus
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pgate = pactive & poly
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psd = pactive - pgate
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ntie = active_in_nwell & nplus
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active_outside_nwell = active - nwell
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nactive = active_outside_nwell & nplus
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ngate = nactive & poly
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nsd = nactive - ngate
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ptie = active_outside_nwell & pplus
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# Device extraction
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# PMOS transistor device extraction
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extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
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"tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell })
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# NMOS transistor device extraction
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extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
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"tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk })
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# Define connectivity for netlist extraction
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# Inter-layer
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connect(psd, contact)
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connect(nsd, contact)
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connect(poly, contact)
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connect(ntie, contact)
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connect(nwell, ntie)
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connect(ptie, contact)
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connect(contact, metal1)
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connect(metal1, via1)
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connect(via1, metal2)
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# Global
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connect_global(bulk, "SUBSTRATE")
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connect_global(ptie, "SUBSTRATE")
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# Compare section
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netlist.flatten_circuit("INVCHAIN")
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netlist.make_top_level_pins
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netlist.purge
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netlist.combine_devices
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netlist.purge_nets
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consider_net_names(false)
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compare
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@ -0,0 +1,540 @@
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#%lvsdb-klayout
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# Layout
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layout(
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top(RINGO)
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unit(0.001)
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# Layer section
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# This section lists the mask layers (drawing or derived) and their connections.
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# Mask layers
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layer(l3 '1/0')
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layer(l4 '5/0')
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layer(l8 '8/0')
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layer(l11 '9/0')
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layer(l12 '10/0')
|
||||
layer(l13 '11/0')
|
||||
layer(l7 '13/0')
|
||||
layer(l2)
|
||||
layer(l9)
|
||||
layer(l6)
|
||||
layer(l10)
|
||||
|
||||
# Mask layer connectivity
|
||||
connect(l3 l3 l9)
|
||||
connect(l4 l4 l8)
|
||||
connect(l8 l4 l8 l11 l2 l9 l6 l10)
|
||||
connect(l11 l8 l11 l12)
|
||||
connect(l12 l11 l12 l13)
|
||||
connect(l13 l12 l13)
|
||||
connect(l2 l8 l2)
|
||||
connect(l9 l3 l8 l9)
|
||||
connect(l6 l8 l6)
|
||||
connect(l10 l8 l10)
|
||||
|
||||
# Global nets and connectivity
|
||||
global(l7 SUBSTRATE)
|
||||
global(l10 SUBSTRATE)
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(ND2X1
|
||||
|
||||
# Circuit boundary
|
||||
rect((-100 250) (2600 7750))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(name(VDD))
|
||||
pin(name(OUT))
|
||||
pin(name(VSS))
|
||||
pin()
|
||||
pin(name(B))
|
||||
pin(name(A))
|
||||
pin(name(BULK))
|
||||
|
||||
)
|
||||
circuit(INVX1
|
||||
|
||||
# Circuit boundary
|
||||
rect((-100 250) (2000 7750))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(name(VDD))
|
||||
pin(name(OUT))
|
||||
pin(name(VSS))
|
||||
pin()
|
||||
pin(name(IN))
|
||||
pin(name(BULK))
|
||||
|
||||
)
|
||||
circuit(INVX2
|
||||
|
||||
# Circuit boundary
|
||||
rect((-100 250) (2600 7750))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(name(IN))
|
||||
pin(name(VDD))
|
||||
pin(name(OUT))
|
||||
pin(name(VSS))
|
||||
pin()
|
||||
pin(name(BULK))
|
||||
|
||||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Circuit boundary
|
||||
rect((600 250) (25800 7750))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1
|
||||
rect(l11 (4040 2950) (610 300))
|
||||
)
|
||||
net(2
|
||||
rect(l11 (5550 2950) (900 300))
|
||||
)
|
||||
net(3
|
||||
rect(l11 (18150 2950) (900 300))
|
||||
)
|
||||
net(4
|
||||
rect(l11 (19950 2950) (900 300))
|
||||
)
|
||||
net(5 name(FB)
|
||||
rect(l11 (21750 2950) (900 300))
|
||||
rect(l11 (-19530 590) (320 320))
|
||||
rect(l11 (17820 -320) (320 320))
|
||||
rect(l12 (-18400 -260) (200 200))
|
||||
rect(l12 (17940 -200) (200 200))
|
||||
rect(l13 (-18040 -300) (17740 400))
|
||||
rect(l13 (-17921 -201) (2 2))
|
||||
rect(l13 (-221 -201) (400 400))
|
||||
rect(l13 (17740 -400) (400 400))
|
||||
)
|
||||
net(6 name(VDD)
|
||||
rect(l3 (1100 4500) (1400 3500))
|
||||
rect(l3 (-1900 -3500) (600 3500))
|
||||
rect(l3 (23300 -3500) (1400 3500))
|
||||
rect(l3 (-100 -3500) (600 3500))
|
||||
rect(l8 (-24690 -1240) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (23220 370) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l11 (-22341 859) (2 2))
|
||||
rect(l11 (-1751 -451) (1200 800))
|
||||
rect(l11 (-750 -1450) (300 1400))
|
||||
rect(l11 (-101 -351) (2 2))
|
||||
rect(l11 (-1251 -401) (600 800))
|
||||
rect(l11 (23400 -800) (1200 800))
|
||||
rect(l11 (-750 -1450) (300 1400))
|
||||
rect(l11 (-101 -351) (2 2))
|
||||
rect(l11 (549 -401) (600 800))
|
||||
rect(l9 (-24850 -1500) (500 1500))
|
||||
rect(l9 (22900 -1500) (500 1500))
|
||||
)
|
||||
net(7 name(OUT)
|
||||
rect(l11 (23440 3840) (320 320))
|
||||
rect(l12 (-260 -260) (200 200))
|
||||
rect(l13 (-101 -101) (2 2))
|
||||
rect(l13 (-201 -201) (400 400))
|
||||
)
|
||||
net(8 name(ENABLE)
|
||||
rect(l11 (2440 2940) (320 320))
|
||||
rect(l12 (-260 -260) (200 200))
|
||||
rect(l13 (-101 -101) (2 2))
|
||||
rect(l13 (-201 -201) (400 400))
|
||||
)
|
||||
net(9 name(VSS)
|
||||
rect(l8 (1710 1610) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (23220 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-22341 -391) (2 2))
|
||||
rect(l11 (-1301 -401) (300 1400))
|
||||
rect(l11 (-750 -1450) (1200 800))
|
||||
rect(l11 (-551 -401) (2 2))
|
||||
rect(l11 (-1251 -401) (600 800))
|
||||
rect(l11 (23850 -750) (300 1400))
|
||||
rect(l11 (-750 -1450) (1200 800))
|
||||
rect(l11 (-551 -401) (2 2))
|
||||
rect(l11 (549 -401) (600 800))
|
||||
rect(l10 (-24850 -800) (500 1500))
|
||||
rect(l10 (22900 -1500) (500 1500))
|
||||
)
|
||||
net(10
|
||||
rect(l11 (7350 2950) (900 300))
|
||||
)
|
||||
net(11
|
||||
rect(l11 (16350 2950) (900 300))
|
||||
)
|
||||
net(12
|
||||
rect(l11 (9150 2950) (900 300))
|
||||
)
|
||||
net(13
|
||||
rect(l11 (10950 2950) (900 300))
|
||||
)
|
||||
net(14
|
||||
rect(l11 (12750 2950) (900 300))
|
||||
)
|
||||
net(15
|
||||
rect(l11 (14550 2950) (900 300))
|
||||
)
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(5 name(FB))
|
||||
pin(6 name(VDD))
|
||||
pin(7 name(OUT))
|
||||
pin(8 name(ENABLE))
|
||||
pin(9 name(VSS))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 ND2X1 location(1800 0)
|
||||
pin(0 6)
|
||||
pin(1 1)
|
||||
pin(2 9)
|
||||
pin(3 6)
|
||||
pin(4 5)
|
||||
pin(5 8)
|
||||
pin(6 9)
|
||||
)
|
||||
circuit(2 INVX1 location(4200 0)
|
||||
pin(0 6)
|
||||
pin(1 2)
|
||||
pin(2 9)
|
||||
pin(3 6)
|
||||
pin(4 1)
|
||||
pin(5 9)
|
||||
)
|
||||
circuit(3 INVX1 location(6000 0)
|
||||
pin(0 6)
|
||||
pin(1 10)
|
||||
pin(2 9)
|
||||
pin(3 6)
|
||||
pin(4 2)
|
||||
pin(5 9)
|
||||
)
|
||||
circuit(4 INVX1 location(16800 0)
|
||||
pin(0 6)
|
||||
pin(1 3)
|
||||
pin(2 9)
|
||||
pin(3 6)
|
||||
pin(4 11)
|
||||
pin(5 9)
|
||||
)
|
||||
circuit(5 INVX1 location(18600 0)
|
||||
pin(0 6)
|
||||
pin(1 4)
|
||||
pin(2 9)
|
||||
pin(3 6)
|
||||
pin(4 3)
|
||||
pin(5 9)
|
||||
)
|
||||
circuit(6 INVX1 location(20400 0)
|
||||
pin(0 6)
|
||||
pin(1 5)
|
||||
pin(2 9)
|
||||
pin(3 6)
|
||||
pin(4 4)
|
||||
pin(5 9)
|
||||
)
|
||||
circuit(7 INVX2 location(22200 0)
|
||||
pin(0 5)
|
||||
pin(1 6)
|
||||
pin(2 7)
|
||||
pin(3 9)
|
||||
pin(4 6)
|
||||
pin(5 9)
|
||||
)
|
||||
circuit(17 INVX1 location(7800 0)
|
||||
pin(0 6)
|
||||
pin(1 12)
|
||||
pin(2 9)
|
||||
pin(3 6)
|
||||
pin(4 10)
|
||||
pin(5 9)
|
||||
)
|
||||
circuit(18 INVX1 location(9600 0)
|
||||
pin(0 6)
|
||||
pin(1 13)
|
||||
pin(2 9)
|
||||
pin(3 6)
|
||||
pin(4 12)
|
||||
pin(5 9)
|
||||
)
|
||||
circuit(19 INVX1 location(11400 0)
|
||||
pin(0 6)
|
||||
pin(1 14)
|
||||
pin(2 9)
|
||||
pin(3 6)
|
||||
pin(4 13)
|
||||
pin(5 9)
|
||||
)
|
||||
circuit(20 INVX1 location(13200 0)
|
||||
pin(0 6)
|
||||
pin(1 15)
|
||||
pin(2 9)
|
||||
pin(3 6)
|
||||
pin(4 14)
|
||||
pin(5 9)
|
||||
)
|
||||
circuit(21 INVX1 location(15000 0)
|
||||
pin(0 6)
|
||||
pin(1 11)
|
||||
pin(2 9)
|
||||
pin(3 6)
|
||||
pin(4 15)
|
||||
pin(5 9)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Reference netlist
|
||||
reference(
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(ND2X1
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(name(VDD))
|
||||
pin(name(OUT))
|
||||
pin(name(VSS))
|
||||
pin(name(NWELL))
|
||||
pin(name(B))
|
||||
pin(name(A))
|
||||
pin(name(BULK))
|
||||
|
||||
)
|
||||
circuit(INVX1
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(name(VDD))
|
||||
pin(name(OUT))
|
||||
pin(name(VSS))
|
||||
pin(name(NWELL))
|
||||
pin(name(IN))
|
||||
pin(name(BULK))
|
||||
|
||||
)
|
||||
circuit(INVX2
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(name(VDD))
|
||||
pin(name(OUT))
|
||||
pin(name(VSS))
|
||||
pin(name(NWELL))
|
||||
pin(name(IN))
|
||||
pin(name(BULK))
|
||||
|
||||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Nets
|
||||
net(1 name(VSS))
|
||||
net(2 name(VDD))
|
||||
net(3 name(FB))
|
||||
net(4 name(ENABLE))
|
||||
net(5 name(OUT))
|
||||
net(6 name('1'))
|
||||
net(7 name('2'))
|
||||
net(8 name('3'))
|
||||
net(9 name('4'))
|
||||
net(10 name('5'))
|
||||
net(11 name('6'))
|
||||
net(12 name('7'))
|
||||
net(13 name('8'))
|
||||
net(14 name('9'))
|
||||
net(15 name('10'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VSS))
|
||||
pin(2 name(VDD))
|
||||
pin(3 name(FB))
|
||||
pin(4 name(ENABLE))
|
||||
pin(5 name(OUT))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 ND2X1 name($1)
|
||||
pin(0 2)
|
||||
pin(1 6)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 3)
|
||||
pin(5 4)
|
||||
pin(6 1)
|
||||
)
|
||||
circuit(2 INVX1 name($2)
|
||||
pin(0 2)
|
||||
pin(1 7)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 6)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(3 INVX1 name($3)
|
||||
pin(0 2)
|
||||
pin(1 8)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 7)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(4 INVX1 name($4)
|
||||
pin(0 2)
|
||||
pin(1 9)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 8)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(5 INVX1 name($5)
|
||||
pin(0 2)
|
||||
pin(1 10)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 9)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(6 INVX1 name($6)
|
||||
pin(0 2)
|
||||
pin(1 11)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 10)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(7 INVX1 name($7)
|
||||
pin(0 2)
|
||||
pin(1 12)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 11)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(8 INVX1 name($8)
|
||||
pin(0 2)
|
||||
pin(1 13)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 12)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(9 INVX1 name($9)
|
||||
pin(0 2)
|
||||
pin(1 14)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 13)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(10 INVX1 name($10)
|
||||
pin(0 2)
|
||||
pin(1 15)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 14)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(11 INVX1 name($11)
|
||||
pin(0 2)
|
||||
pin(1 3)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 15)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(12 INVX2 name($12)
|
||||
pin(0 2)
|
||||
pin(1 5)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 3)
|
||||
pin(5 1)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Cross reference
|
||||
xref(
|
||||
circuit(INVX1 INVX1 match
|
||||
xref(
|
||||
pin(3 3 match)
|
||||
pin(5 5 match)
|
||||
pin(4 4 match)
|
||||
pin(1 1 match)
|
||||
pin(0 0 match)
|
||||
pin(2 2 match)
|
||||
)
|
||||
)
|
||||
circuit(INVX2 INVX2 match
|
||||
xref(
|
||||
pin(4 3 match)
|
||||
pin(5 5 match)
|
||||
pin(0 4 match)
|
||||
pin(2 1 match)
|
||||
pin(1 0 match)
|
||||
pin(3 2 match)
|
||||
)
|
||||
)
|
||||
circuit(ND2X1 ND2X1 match
|
||||
xref(
|
||||
pin(3 3 match)
|
||||
pin(5 5 match)
|
||||
pin(4 4 match)
|
||||
pin(6 6 match)
|
||||
pin(1 1 match)
|
||||
pin(0 0 match)
|
||||
pin(2 2 match)
|
||||
)
|
||||
)
|
||||
circuit(RINGO RINGO match
|
||||
xref(
|
||||
net(1 6 match)
|
||||
net(4 15 match)
|
||||
net(2 7 match)
|
||||
net(10 8 match)
|
||||
net(12 9 match)
|
||||
net(13 10 match)
|
||||
net(14 11 match)
|
||||
net(15 12 match)
|
||||
net(11 13 match)
|
||||
net(3 14 match)
|
||||
net(8 4 match)
|
||||
net(5 3 match)
|
||||
net(7 5 match)
|
||||
net(6 2 match)
|
||||
net(9 1 match)
|
||||
pin(3 3 match)
|
||||
pin(0 2 match)
|
||||
pin(2 4 match)
|
||||
pin(1 1 match)
|
||||
pin(4 0 match)
|
||||
circuit(2 2 match)
|
||||
circuit(3 3 match)
|
||||
circuit(17 4 match)
|
||||
circuit(18 5 match)
|
||||
circuit(19 6 match)
|
||||
circuit(20 7 match)
|
||||
circuit(21 8 match)
|
||||
circuit(4 9 match)
|
||||
circuit(5 10 match)
|
||||
circuit(6 11 match)
|
||||
circuit(7 12 match)
|
||||
circuit(1 1 match)
|
||||
)
|
||||
)
|
||||
)
|
||||
Loading…
Reference in New Issue