mirror of https://github.com/KLayout/klayout.git
LVS: can be used anywhere now: tolerance and join_symmetric_nets
This commit is contained in:
Matthias Koefferlein
parent
c24c0933bf
commit
24afd571f0
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@ -4477,7 +4477,9 @@ NetlistComparer::join_symmetric_nets (db::Circuit *circuit)
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std::map<const db::Circuit *, CircuitMapper> circuit_and_pin_mapping;
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db::NetGraph graph;
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graph.build (circuit, *mp_device_categorizer, *mp_circuit_categorizer, device_filter, &circuit_and_pin_mapping, &circuit_pin_mapper);
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db::CircuitCategorizer circuit_categorizer;
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db::DeviceCategorizer device_categorizer;
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graph.build (circuit, device_categorizer, circuit_categorizer, device_filter, &circuit_and_pin_mapping, &circuit_pin_mapper);
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// sort the nodes so we can easily identify the identical ones (in terms of topology)
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// nodes are identical if the attached devices and circuits are of the same kind and with the same parameters
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@ -64,10 +64,8 @@ module DRC
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def initialize(engine)
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@engine = engine
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@connect_implicit = []
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@connect_implicit_per_cell = {}
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@connect_explicit = []
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@connect_explicit_per_cell = {}
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@pre_extract_config = []
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@post_extract_config = []
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@l2n = nil
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@lnum = 0
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@device_scaling = 1.0
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@ -239,10 +237,8 @@ module DRC
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# See \connect for more details.
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def clear_connections
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@connect_implicit = []
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@connect_implicit_per_cell = {}
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@connect_explicit = []
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@connect_explicit_per_cell = {}
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@pre_extract_config = []
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@post_extract_config = []
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_clear_data
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end
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@ -277,11 +273,10 @@ module DRC
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if arg2
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(arg2.is_a?(String) && arg2 != "") || raise("The second argument has to be a non-empty string")
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arg1.is_a?(String) || raise("The first argument has to be a string")
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@connect_implicit_per_cell[arg1] ||= []
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@connect_implicit_per_cell[arg1] << arg2
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@pre_extract_config << lambda { |l2n| l2n.join_net_names(arg1, arg2) }
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else
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arg1.is_a?(String) || raise("The argument has to be a string")
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@connect_implicit << arg1
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@pre_extract_config << lambda { |l2n| l2n.join_net_names(arg1) }
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end
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end
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@ -338,11 +333,10 @@ module DRC
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arg2.is_a?(Array) || raise("The second argument has to be an array of strings")
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arg2.find { |a| !a.is_a?(String) } && raise("The second argument has to be an array of strings")
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arg1.is_a?(String) || raise("The first argument has to be a string")
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@connect_explicit_per_cell[arg1] ||= []
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@connect_explicit_per_cell[arg1] << arg2
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@pre_extract_config << lambda { |l2n| l2n.join_nets(arg1, arg2) }
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else
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arg1.is_a?(String) || raise("The argument has to be a string")
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@connect_explicit << arg1
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@pre_extract_config << lambda { |l2n| l2n.join_nets(arg1) }
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end
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end
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@ -563,30 +557,21 @@ module DRC
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# run extraction in a timed environment
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if ! @l2n.is_extracted?
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# configure implicit net connections
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@l2n.clear_join_net_names
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@connect_implicit.each do |label_pattern|
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@l2n.join_net_names(label_pattern)
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end
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@connect_implicit_per_cell.each do |cell_pattern,label_pattern|
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label_pattern.each do |lp|
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@l2n.join_net_names(cell_pattern, lp)
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end
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end
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# configure explicit net connections
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@l2n.clear_join_nets
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@connect_explicit.each do |names|
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@l2n.join_nets(names)
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end
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@connect_explicit_per_cell.each do |cell_pattern,name_lists|
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name_lists.each do |names|
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@l2n.join_nets(cell_pattern, names)
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end
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# configure the netter
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@pre_extract_config.each do |cfg|
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cfg.call(@l2n)
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end
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@engine._cmd(@l2n, :extract_netlist)
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# configure the netter, post-extraction
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@post_extract_config.each do |cfg|
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cfg.call(@l2n)
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end
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end
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@l2n
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@ -49,6 +49,7 @@ module LVS
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def initialize(engine)
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super
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@comparer_config = []
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@comparer_miniconfig = []
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end
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def _make_data
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@ -140,7 +141,18 @@ module LVS
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abs_tol ||= 0.0
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rel_tol ||= 0.0
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dc = netlist.device_class_by_name(device_class_name)
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if self._l2n_data
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# already extracted
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self._tolerance(self._l2n_data, device_class_name, parameter_name, abs_tol, rel_tol)
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else
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@post_extract_config << lambda { |l2n| self._tolerance(l2n, device_class_name, parameter_name, abs_tol, rel_tol) }
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end
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end
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def _tolerance(l2n, device_class_name, parameter_name, abs_tol, rel_tol)
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dc = l2n.netlist.device_class_by_name(device_class_name)
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if dc && dc.has_parameter?(parameter_name)
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ep = RBA::EqualDeviceParameters::new(dc.parameter_id(parameter_name), abs_tol, rel_tol)
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if dc.equal_parameters == nil
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@ -250,13 +262,25 @@ module LVS
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circuit_pattern.is_a?(String) || raise("Circuit pattern argument of 'join_symmetric_nets' must be a string")
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comparer = self._comparer
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if self._l2n_data
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# already extracted
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self._join_symmetric_nets(self._l2n_data, circuit_pattern)
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else
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@post_extract_config << lambda { |l2n| self._join_symmetric_nets(l2n, circuit_pattern) }
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end
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netlist || raise("No netlist present (not extracted?)")
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netlist.circuits_by_name(circuit_pattern).each do |c|
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end
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def _join_symmetric_nets(l2n, circuit_pattern)
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comparer = self._comparer_mini
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l2n.netlist.circuits_by_name(circuit_pattern).each do |c|
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comparer.join_symmetric_nets(c)
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end
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comparer._destroy
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end
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def _comparer
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@ -272,6 +296,19 @@ module LVS
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end
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def _comparer_mini
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comparer = RBA::NetlistComparer::new
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# execute the configuration commands
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@comparer_miniconfig.each do |cc|
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cc.call(comparer)
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end
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return comparer
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end
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def _ensure_two_netlists
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netlist || raise("No netlist present (not extracted?)")
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@ -589,6 +626,7 @@ module LVS
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def min_caps(value)
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v = value.to_f
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@comparer_config << lambda { |comparer| comparer.min_capacitance = v }
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@comparer_miniconfig << lambda { |comparer| comparer.min_capacitance = v }
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end
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# %LVS%
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@ -601,6 +639,7 @@ module LVS
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def max_res(value)
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v = value.to_f
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@comparer_config << lambda { |comparer| comparer.max_resistance = v }
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@comparer_miniconfig << lambda { |comparer| comparer.max_resistance = v }
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end
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# %LVS%
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@ -86,6 +86,11 @@ TEST(1b_simple_with_tolerance)
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run_test (_this, "ringo_simple_with_tol", "ringo.gds");
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}
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TEST(1c_simple_with_tolerance_early)
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{
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run_test (_this, "ringo_simple_with_tol_early", "ringo.gds");
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}
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TEST(2_simple_io)
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{
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run_test (_this, "ringo_simple_io", "ringo.gds");
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@ -200,6 +205,11 @@ TEST(22_split_gate)
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run_test (_this, "nand2_split_gate", "nand2_split_gate.oas");
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}
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TEST(22b_split_gate_early)
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{
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run_test (_this, "nand2_split_gate_early", "nand2_split_gate.oas");
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}
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// empty gds
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TEST(23_issue709)
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{
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@ -0,0 +1,23 @@
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* Extracted by KLayout
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* cell NAND2_WITH_DIODES
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* pin B
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* pin A
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* pin OUT
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* pin VDD
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* pin VSS
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.SUBCKT NAND2_WITH_DIODES 1 2 4 5 6
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* net 1 B
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* net 2 A
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* net 4 OUT
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* net 5 VDD
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* net 6 VSS
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* device instance $1 r0 *1 1.025,4.95 PMOS
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M$1 5 1 4 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U
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* device instance $2 r0 *1 1.775,4.95 PMOS
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M$2 4 2 5 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U
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* device instance $3 r0 *1 1.025,2 NMOS
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M$3 6 1 3 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U
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* device instance $4 r0 *1 1.775,2 NMOS
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M$4 3 2 4 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U
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.ENDS NAND2_WITH_DIODES
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@ -0,0 +1,23 @@
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* Extracted by KLayout
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* cell NAND2_WITH_DIODES
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* pin B
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* pin A
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* pin OUT
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* pin VDD
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* pin VSS
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.SUBCKT NAND2_WITH_DIODES 1 2 4 5 6
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* net 1 B
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* net 2 A
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* net 4 OUT
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* net 5 VDD
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* net 6 VSS
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* device instance $1 r0 *1 1.025,4.95 PMOS
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M$1 5 1 4 5 PMOS L=0.25U W=1.5U AS=0.675P AD=0.375P PS=3.9U PD=2U
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* device instance $2 r0 *1 1.775,4.95 PMOS
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M$2 4 2 5 5 PMOS L=0.25U W=1.5U AS=0.375P AD=0.675P PS=2U PD=3.9U
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* device instance $3 r0 *1 1.025,0.65 NMOS
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M$3 6 1 3 6 NMOS L=0.25U W=1.8U AS=0.81P AD=0.45P PS=5.4U PD=2.8U
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* device instance $4 r0 *1 1.775,0.65 NMOS
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M$4 3 2 4 6 NMOS L=0.25U W=1.8U AS=0.45P AD=0.81P PS=2.8U PD=5.4U
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.ENDS NAND2_WITH_DIODES
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@ -0,0 +1,85 @@
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source($lvs_test_source, "NAND2_WITH_DIODES")
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report_lvs($lvs_test_target_lvsdb, true)
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target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
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schematic("nand2_split_gate_schematic.cir")
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join_symmetric_nets("*")
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deep
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# Reports generated
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# Drawing layers
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nwell = input(1, 0)
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active = input(2, 0)
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pplus = input(3, 0)
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nplus = input(4, 0)
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poly = input(5, 0)
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contact = input(6, 0)
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metal1 = input(7, 0)
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metal1_lbl = labels(7, 1)
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via1 = input(8, 0)
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metal2 = input(9, 0)
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metal2_lbl = labels(9, 1)
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# Bulk layer for terminal provisioning
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bulk = polygon_layer
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# Computed layers
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active_in_nwell = active & nwell
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pactive = active_in_nwell & pplus
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pgate = pactive & poly
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psd = pactive - pgate
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ntie = active_in_nwell & nplus
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active_outside_nwell = active - nwell
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nactive = active_outside_nwell & nplus
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ngate = nactive & poly
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nsd = nactive - ngate
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ptie = active_outside_nwell & pplus
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# Device extraction
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# PMOS transistor device extraction
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extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
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"tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell })
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# NMOS transistor device extraction
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extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
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"tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk })
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# Define connectivity for netlist extraction
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# Inter-layer
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connect(psd, contact)
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connect(nsd, contact)
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connect(poly, contact)
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connect(ntie, contact)
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connect(nwell, ntie)
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connect(ptie, contact)
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connect(contact, metal1)
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connect(metal1, metal1_lbl) # attaches labels
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connect(metal1, via1)
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connect(via1, metal2)
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connect(metal2, metal2_lbl) # attaches labels
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# Global
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connect_global(bulk, "SUBSTRATE")
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connect_global(ptie, "SUBSTRATE")
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# Extract, simplify
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netlist
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netlist.simplify
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# Compare section
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compare
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@ -0,0 +1,407 @@
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#%lvsdb-klayout
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# Layout
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layout(
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top(NAND2_WITH_DIODES)
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unit(0.001)
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# Layer section
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# This section lists the mask layers (drawing or derived) and their connections.
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# Mask layers
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layer(l3 'NWELL (1/0)')
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layer(l4 'POLY (5/0)')
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layer(l8 'CONTACT (6/0)')
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layer(l11 'METAL1 (7/0)')
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layer(l12 'METAL1_LABEL (7/1)')
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layer(l13 'VIA1 (8/0)')
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layer(l14 'METAL2 (9/0)')
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layer(l15 'METAL2_LABEL (9/1)')
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layer(l7)
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layer(l2)
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layer(l9)
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layer(l6)
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layer(l10)
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# Mask layer connectivity
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connect(l3 l3 l9)
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connect(l4 l4 l8)
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connect(l8 l4 l8 l11 l2 l9 l6 l10)
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connect(l11 l8 l11 l12 l13)
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connect(l12 l11)
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connect(l13 l11 l13 l14)
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connect(l14 l13 l14 l15)
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connect(l15 l14)
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connect(l7 l7)
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connect(l2 l8 l2)
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connect(l9 l3 l8 l9)
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connect(l6 l8 l6)
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connect(l10 l8 l10)
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# Global nets and connectivity
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global(l7 SUBSTRATE)
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global(l10 SUBSTRATE)
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# Device class section
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class(PMOS MOS4)
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class(NMOS MOS4)
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# Device abstracts section
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# Device abstracts list the pin shapes of the devices.
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device(D$PMOS PMOS
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terminal(S
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rect(l2 (-575 -750) (450 1500))
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)
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terminal(G
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rect(l4 (-125 -750) (250 1500))
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)
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terminal(D
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rect(l2 (125 -750) (500 1500))
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)
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terminal(B
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rect(l3 (-125 -750) (250 1500))
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)
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)
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device(D$PMOS$1 PMOS
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terminal(S
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rect(l2 (-625 -750) (500 1500))
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)
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terminal(G
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rect(l4 (-125 -750) (250 1500))
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)
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terminal(D
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rect(l2 (125 -750) (450 1500))
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)
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terminal(B
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rect(l3 (-125 -750) (250 1500))
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)
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)
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device(D$NMOS NMOS
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terminal(S
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rect(l6 (-575 -450) (450 900))
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)
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terminal(G
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rect(l4 (-125 -450) (250 900))
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)
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terminal(D
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rect(l6 (125 -450) (500 900))
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)
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terminal(B
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rect(l7 (-125 -450) (250 900))
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)
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)
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device(D$NMOS$1 NMOS
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terminal(S
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rect(l6 (-625 -450) (500 900))
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)
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terminal(G
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rect(l4 (-125 -450) (250 900))
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)
|
||||
terminal(D
|
||||
rect(l6 (125 -450) (450 900))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -450) (250 900))
|
||||
)
|
||||
)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(NAND2_WITH_DIODES
|
||||
|
||||
# Circuit boundary
|
||||
rect((0 0) (3750 6150))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(B)
|
||||
rect(l4 (350 2750) (550 400))
|
||||
rect(l4 (0 -2050) (250 3100))
|
||||
rect(l4 (-250 0) (250 1650))
|
||||
rect(l4 (-250 -5800) (250 1050))
|
||||
rect(l4 (-250 300) (250 1050))
|
||||
rect(l8 (-700 400) (200 200))
|
||||
rect(l11 (-300 -300) (400 400))
|
||||
text(l12 B (-200 -200))
|
||||
)
|
||||
net(2 name(A)
|
||||
rect(l4 (1900 3400) (550 400))
|
||||
rect(l4 (-800 -2700) (250 3100))
|
||||
rect(l4 (-250 0) (250 1650))
|
||||
rect(l4 (-250 -5800) (250 1050))
|
||||
rect(l4 (-250 300) (250 1050))
|
||||
rect(l8 (250 1050) (200 200))
|
||||
rect(l11 (-300 -300) (400 400))
|
||||
text(l12 A (-200 -200))
|
||||
)
|
||||
net(3
|
||||
rect(l8 (1300 300) (200 200))
|
||||
rect(l8 (-200 -200) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l8 (-200 -200) (200 200))
|
||||
rect(l8 (-200 650) (200 200))
|
||||
rect(l8 (-200 -200) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l8 (-200 -200) (200 200))
|
||||
rect(l11 (-250 -2150) (300 900))
|
||||
rect(l11 (-300 -900) (300 850))
|
||||
rect(l11 (-300 500) (300 900))
|
||||
rect(l11 (-300 -900) (300 850))
|
||||
rect(l6 (-400 -2200) (500 900))
|
||||
rect(l6 (-500 450) (500 900))
|
||||
)
|
||||
net(4 name(OUT)
|
||||
rect(l8 (2050 300) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l8 (-200 650) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l8 (-950 2000) (200 200))
|
||||
rect(l8 (-200 -200) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l8 (-200 -200) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l8 (-200 -200) (200 200))
|
||||
rect(l11 (500 -5350) (300 850))
|
||||
rect(l11 (-300 -50) (300 1950))
|
||||
rect(l11 (-300 -1400) (300 850))
|
||||
rect(l11 (-300 300) (450 400))
|
||||
rect(l11 (-1200 -300) (1050 300))
|
||||
rect(l11 (-1050 1150) (300 1400))
|
||||
rect(l11 (-300 -2700) (300 1950))
|
||||
text(l12 OUT (700 -2000))
|
||||
rect(l2 (-1100 1300) (500 1500))
|
||||
rect(l6 (250 -5500) (450 900))
|
||||
rect(l6 (-450 450) (450 900))
|
||||
)
|
||||
net(5 name(VDD)
|
||||
rect(l3 (0 2950) (3750 3200))
|
||||
rect(l8 (-3200 -1800) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l8 (1300 -1200) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l8 (700 -800) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l11 (-2650 -1200) (300 1600))
|
||||
rect(l11 (1200 -1600) (300 1600))
|
||||
rect(l11 (600 -1200) (300 1200))
|
||||
rect(l13 (-2650 -800) (200 200))
|
||||
rect(l13 (-200 300) (200 200))
|
||||
rect(l13 (1300 -700) (200 200))
|
||||
rect(l13 (-200 300) (200 200))
|
||||
rect(l13 (700 -700) (200 200))
|
||||
rect(l13 (-200 300) (200 200))
|
||||
rect(l14 (-3150 -850) (3750 1000))
|
||||
text(l15 VDD (-100 -850))
|
||||
rect(l2 (-3200 -850) (450 1500))
|
||||
rect(l2 (1000 -1500) (450 1500))
|
||||
rect(l9 (400 -1200) (600 1200))
|
||||
)
|
||||
net(6 name(VSS)
|
||||
rect(l8 (550 1650) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l8 (-200 -2050) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l8 (2200 -550) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l11 (-2650 -50) (300 1350))
|
||||
rect(l11 (-300 -2400) (300 1050))
|
||||
rect(l11 (2100 -1050) (300 1200))
|
||||
rect(l13 (-2650 -1100) (200 200))
|
||||
rect(l13 (-200 300) (200 200))
|
||||
rect(l13 (2200 -700) (200 200))
|
||||
rect(l13 (-200 300) (200 200))
|
||||
rect(l14 (-3150 -850) (3750 1000))
|
||||
text(l15 VSS (-100 -850))
|
||||
rect(l6 (-3200 1400) (450 900))
|
||||
rect(l6 (-450 -2250) (450 900))
|
||||
rect(l10 (1850 -900) (600 1200))
|
||||
)
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(B))
|
||||
pin(2 name(A))
|
||||
pin(4 name(OUT))
|
||||
pin(5 name(VDD))
|
||||
pin(6 name(VSS))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 D$PMOS
|
||||
location(1025 4950)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.675)
|
||||
param(AD 0.375)
|
||||
param(PS 3.9)
|
||||
param(PD 2)
|
||||
terminal(S 5)
|
||||
terminal(G 1)
|
||||
terminal(D 4)
|
||||
terminal(B 5)
|
||||
)
|
||||
device(2 D$PMOS$1
|
||||
location(1775 4950)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.375)
|
||||
param(AD 0.675)
|
||||
param(PS 2)
|
||||
param(PD 3.9)
|
||||
terminal(S 4)
|
||||
terminal(G 2)
|
||||
terminal(D 5)
|
||||
terminal(B 5)
|
||||
)
|
||||
device(3 D$NMOS
|
||||
device(D$NMOS location(0 -1350))
|
||||
connect(0 S S)
|
||||
connect(1 S S)
|
||||
connect(0 G G)
|
||||
connect(1 G G)
|
||||
connect(0 D D)
|
||||
connect(1 D D)
|
||||
connect(0 B B)
|
||||
connect(1 B B)
|
||||
location(1025 2000)
|
||||
param(L 0.25)
|
||||
param(W 1.8)
|
||||
param(AS 0.81)
|
||||
param(AD 0.45)
|
||||
param(PS 5.4)
|
||||
param(PD 2.8)
|
||||
terminal(S 6)
|
||||
terminal(G 1)
|
||||
terminal(D 3)
|
||||
terminal(B 6)
|
||||
)
|
||||
device(4 D$NMOS$1
|
||||
device(D$NMOS$1 location(0 -1350))
|
||||
connect(0 S S)
|
||||
connect(1 S S)
|
||||
connect(0 G G)
|
||||
connect(1 G G)
|
||||
connect(0 D D)
|
||||
connect(1 D D)
|
||||
connect(0 B B)
|
||||
connect(1 B B)
|
||||
location(1775 2000)
|
||||
param(L 0.25)
|
||||
param(W 1.8)
|
||||
param(AS 0.45)
|
||||
param(AD 0.81)
|
||||
param(PS 2.8)
|
||||
param(PD 5.4)
|
||||
terminal(S 3)
|
||||
terminal(G 2)
|
||||
terminal(D 4)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Reference netlist
|
||||
reference(
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(NAND2_WITH_DIODES
|
||||
|
||||
# Nets
|
||||
net(1 name(A))
|
||||
net(2 name(B))
|
||||
net(3 name(OUT))
|
||||
net(4 name(VSS))
|
||||
net(5 name(VDD))
|
||||
net(6 name($1))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(A))
|
||||
pin(2 name(B))
|
||||
pin(3 name(OUT))
|
||||
pin(4 name(VSS))
|
||||
pin(5 name(VDD))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name('1')
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 5)
|
||||
terminal(G 2)
|
||||
terminal(D 3)
|
||||
terminal(B 5)
|
||||
)
|
||||
device(2 PMOS
|
||||
name('2')
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 5)
|
||||
terminal(G 1)
|
||||
terminal(D 3)
|
||||
terminal(B 5)
|
||||
)
|
||||
device(3 NMOS
|
||||
name('3')
|
||||
param(L 0.25)
|
||||
param(W 1.8)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 4)
|
||||
terminal(G 2)
|
||||
terminal(D 6)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(4 NMOS
|
||||
name('4')
|
||||
param(L 0.25)
|
||||
param(W 1.8)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 6)
|
||||
terminal(G 1)
|
||||
terminal(D 3)
|
||||
terminal(B 4)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Cross reference
|
||||
xref(
|
||||
circuit(NAND2_WITH_DIODES NAND2_WITH_DIODES match
|
||||
xref(
|
||||
net(3 6 match)
|
||||
net(2 1 match)
|
||||
net(1 2 match)
|
||||
net(4 3 match)
|
||||
net(5 5 match)
|
||||
net(6 4 match)
|
||||
pin(1 0 match)
|
||||
pin(0 1 match)
|
||||
pin(2 2 match)
|
||||
pin(3 4 match)
|
||||
pin(4 3 match)
|
||||
device(3 3 match)
|
||||
device(4 4 match)
|
||||
device(1 1 match)
|
||||
device(2 2 match)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,407 @@
|
|||
#%lvsdb-klayout
|
||||
|
||||
# Layout
|
||||
layout(
|
||||
top(NAND2_WITH_DIODES)
|
||||
unit(0.001)
|
||||
|
||||
# Layer section
|
||||
# This section lists the mask layers (drawing or derived) and their connections.
|
||||
|
||||
# Mask layers
|
||||
layer(l3 'NWELL (1/0)')
|
||||
layer(l4 'POLY (5/0)')
|
||||
layer(l8 'CONTACT (6/0)')
|
||||
layer(l11 'METAL1 (7/0)')
|
||||
layer(l12 'METAL1_LABEL (7/1)')
|
||||
layer(l13 'VIA1 (8/0)')
|
||||
layer(l14 'METAL2 (9/0)')
|
||||
layer(l15 'METAL2_LABEL (9/1)')
|
||||
layer(l7)
|
||||
layer(l2)
|
||||
layer(l9)
|
||||
layer(l6)
|
||||
layer(l10)
|
||||
|
||||
# Mask layer connectivity
|
||||
connect(l3 l3 l9)
|
||||
connect(l4 l4 l8)
|
||||
connect(l8 l4 l8 l11 l2 l9 l6 l10)
|
||||
connect(l11 l8 l11 l12 l13)
|
||||
connect(l12 l11)
|
||||
connect(l13 l11 l13 l14)
|
||||
connect(l14 l13 l14 l15)
|
||||
connect(l15 l14)
|
||||
connect(l7 l7)
|
||||
connect(l2 l8 l2)
|
||||
connect(l9 l3 l8 l9)
|
||||
connect(l6 l8 l6)
|
||||
connect(l10 l8 l10)
|
||||
|
||||
# Global nets and connectivity
|
||||
global(l7 SUBSTRATE)
|
||||
global(l10 SUBSTRATE)
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Device abstracts section
|
||||
# Device abstracts list the pin shapes of the devices.
|
||||
device(D$PMOS PMOS
|
||||
terminal(S
|
||||
rect(l2 (-575 -750) (450 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l2 (125 -750) (500 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$PMOS$1 PMOS
|
||||
terminal(S
|
||||
rect(l2 (-625 -750) (500 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l2 (125 -750) (450 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$NMOS NMOS
|
||||
terminal(S
|
||||
rect(l6 (-575 -450) (450 900))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -450) (250 900))
|
||||
)
|
||||
terminal(D
|
||||
rect(l6 (125 -450) (500 900))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -450) (250 900))
|
||||
)
|
||||
)
|
||||
device(D$NMOS$1 NMOS
|
||||
terminal(S
|
||||
rect(l6 (-625 -450) (500 900))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -450) (250 900))
|
||||
)
|
||||
terminal(D
|
||||
rect(l6 (125 -450) (450 900))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -450) (250 900))
|
||||
)
|
||||
)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(NAND2_WITH_DIODES
|
||||
|
||||
# Circuit boundary
|
||||
rect((0 0) (3750 6150))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(B)
|
||||
rect(l4 (350 2750) (550 400))
|
||||
rect(l4 (0 -2050) (250 3100))
|
||||
rect(l4 (-250 0) (250 1650))
|
||||
rect(l4 (-250 -5800) (250 1050))
|
||||
rect(l4 (-250 300) (250 1050))
|
||||
rect(l8 (-700 400) (200 200))
|
||||
rect(l11 (-300 -300) (400 400))
|
||||
text(l12 B (-200 -200))
|
||||
)
|
||||
net(2 name(A)
|
||||
rect(l4 (1900 3400) (550 400))
|
||||
rect(l4 (-800 -2700) (250 3100))
|
||||
rect(l4 (-250 0) (250 1650))
|
||||
rect(l4 (-250 -5800) (250 1050))
|
||||
rect(l4 (-250 300) (250 1050))
|
||||
rect(l8 (250 1050) (200 200))
|
||||
rect(l11 (-300 -300) (400 400))
|
||||
text(l12 A (-200 -200))
|
||||
)
|
||||
net(3
|
||||
rect(l8 (1300 300) (200 200))
|
||||
rect(l8 (-200 -200) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l8 (-200 -200) (200 200))
|
||||
rect(l8 (-200 650) (200 200))
|
||||
rect(l8 (-200 -200) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l8 (-200 -200) (200 200))
|
||||
rect(l11 (-250 -2150) (300 900))
|
||||
rect(l11 (-300 -900) (300 850))
|
||||
rect(l11 (-300 500) (300 900))
|
||||
rect(l11 (-300 -900) (300 850))
|
||||
rect(l6 (-400 -2200) (500 900))
|
||||
rect(l6 (-500 450) (500 900))
|
||||
)
|
||||
net(4 name(OUT)
|
||||
rect(l8 (2050 300) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l8 (-200 650) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l8 (-950 2000) (200 200))
|
||||
rect(l8 (-200 -200) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l8 (-200 -200) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l8 (-200 -200) (200 200))
|
||||
rect(l11 (500 -5350) (300 850))
|
||||
rect(l11 (-300 -50) (300 1950))
|
||||
rect(l11 (-300 -1400) (300 850))
|
||||
rect(l11 (-300 300) (450 400))
|
||||
rect(l11 (-1200 -300) (1050 300))
|
||||
rect(l11 (-1050 1150) (300 1400))
|
||||
rect(l11 (-300 -2700) (300 1950))
|
||||
text(l12 OUT (700 -2000))
|
||||
rect(l2 (-1100 1300) (500 1500))
|
||||
rect(l6 (250 -5500) (450 900))
|
||||
rect(l6 (-450 450) (450 900))
|
||||
)
|
||||
net(5 name(VDD)
|
||||
rect(l3 (0 2950) (3750 3200))
|
||||
rect(l8 (-3200 -1800) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l8 (1300 -1200) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l8 (700 -800) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l11 (-2650 -1200) (300 1600))
|
||||
rect(l11 (1200 -1600) (300 1600))
|
||||
rect(l11 (600 -1200) (300 1200))
|
||||
rect(l13 (-2650 -800) (200 200))
|
||||
rect(l13 (-200 300) (200 200))
|
||||
rect(l13 (1300 -700) (200 200))
|
||||
rect(l13 (-200 300) (200 200))
|
||||
rect(l13 (700 -700) (200 200))
|
||||
rect(l13 (-200 300) (200 200))
|
||||
rect(l14 (-3150 -850) (3750 1000))
|
||||
text(l15 VDD (-100 -850))
|
||||
rect(l2 (-3200 -850) (450 1500))
|
||||
rect(l2 (1000 -1500) (450 1500))
|
||||
rect(l9 (400 -1200) (600 1200))
|
||||
)
|
||||
net(6 name(VSS)
|
||||
rect(l8 (550 1650) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l8 (-200 -2050) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l8 (2200 -550) (200 200))
|
||||
rect(l8 (-200 300) (200 200))
|
||||
rect(l11 (-2650 -50) (300 1350))
|
||||
rect(l11 (-300 -2400) (300 1050))
|
||||
rect(l11 (2100 -1050) (300 1200))
|
||||
rect(l13 (-2650 -1100) (200 200))
|
||||
rect(l13 (-200 300) (200 200))
|
||||
rect(l13 (2200 -700) (200 200))
|
||||
rect(l13 (-200 300) (200 200))
|
||||
rect(l14 (-3150 -850) (3750 1000))
|
||||
text(l15 VSS (-100 -850))
|
||||
rect(l6 (-3200 1400) (450 900))
|
||||
rect(l6 (-450 -2250) (450 900))
|
||||
rect(l10 (1850 -900) (600 1200))
|
||||
)
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(B))
|
||||
pin(2 name(A))
|
||||
pin(4 name(OUT))
|
||||
pin(5 name(VDD))
|
||||
pin(6 name(VSS))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 D$PMOS
|
||||
location(1025 4950)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.675)
|
||||
param(AD 0.375)
|
||||
param(PS 3.9)
|
||||
param(PD 2)
|
||||
terminal(S 5)
|
||||
terminal(G 1)
|
||||
terminal(D 4)
|
||||
terminal(B 5)
|
||||
)
|
||||
device(2 D$PMOS$1
|
||||
location(1775 4950)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.375)
|
||||
param(AD 0.675)
|
||||
param(PS 2)
|
||||
param(PD 3.9)
|
||||
terminal(S 4)
|
||||
terminal(G 2)
|
||||
terminal(D 5)
|
||||
terminal(B 5)
|
||||
)
|
||||
device(3 D$NMOS
|
||||
device(D$NMOS location(0 1350))
|
||||
connect(0 S S)
|
||||
connect(1 S S)
|
||||
connect(0 G G)
|
||||
connect(1 G G)
|
||||
connect(0 D D)
|
||||
connect(1 D D)
|
||||
connect(0 B B)
|
||||
connect(1 B B)
|
||||
location(1025 650)
|
||||
param(L 0.25)
|
||||
param(W 1.8)
|
||||
param(AS 0.81)
|
||||
param(AD 0.45)
|
||||
param(PS 5.4)
|
||||
param(PD 2.8)
|
||||
terminal(S 6)
|
||||
terminal(G 1)
|
||||
terminal(D 3)
|
||||
terminal(B 6)
|
||||
)
|
||||
device(4 D$NMOS$1
|
||||
device(D$NMOS$1 location(0 1350))
|
||||
connect(0 S S)
|
||||
connect(1 S S)
|
||||
connect(0 G G)
|
||||
connect(1 G G)
|
||||
connect(0 D D)
|
||||
connect(1 D D)
|
||||
connect(0 B B)
|
||||
connect(1 B B)
|
||||
location(1775 650)
|
||||
param(L 0.25)
|
||||
param(W 1.8)
|
||||
param(AS 0.45)
|
||||
param(AD 0.81)
|
||||
param(PS 2.8)
|
||||
param(PD 5.4)
|
||||
terminal(S 3)
|
||||
terminal(G 2)
|
||||
terminal(D 4)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Reference netlist
|
||||
reference(
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(NAND2_WITH_DIODES
|
||||
|
||||
# Nets
|
||||
net(1 name(A))
|
||||
net(2 name(B))
|
||||
net(3 name(OUT))
|
||||
net(4 name(VSS))
|
||||
net(5 name(VDD))
|
||||
net(6 name($1))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(A))
|
||||
pin(2 name(B))
|
||||
pin(3 name(OUT))
|
||||
pin(4 name(VSS))
|
||||
pin(5 name(VDD))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name('1')
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 5)
|
||||
terminal(G 2)
|
||||
terminal(D 3)
|
||||
terminal(B 5)
|
||||
)
|
||||
device(2 PMOS
|
||||
name('2')
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 5)
|
||||
terminal(G 1)
|
||||
terminal(D 3)
|
||||
terminal(B 5)
|
||||
)
|
||||
device(3 NMOS
|
||||
name('3')
|
||||
param(L 0.25)
|
||||
param(W 1.8)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 4)
|
||||
terminal(G 2)
|
||||
terminal(D 6)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(4 NMOS
|
||||
name('4')
|
||||
param(L 0.25)
|
||||
param(W 1.8)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 6)
|
||||
terminal(G 1)
|
||||
terminal(D 3)
|
||||
terminal(B 4)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Cross reference
|
||||
xref(
|
||||
circuit(NAND2_WITH_DIODES NAND2_WITH_DIODES match
|
||||
xref(
|
||||
net(3 6 match)
|
||||
net(2 1 match)
|
||||
net(1 2 match)
|
||||
net(4 3 match)
|
||||
net(5 5 match)
|
||||
net(6 4 match)
|
||||
pin(1 0 match)
|
||||
pin(0 1 match)
|
||||
pin(2 2 match)
|
||||
pin(3 4 match)
|
||||
pin(4 3 match)
|
||||
device(3 3 match)
|
||||
device(4 4 match)
|
||||
device(1 1 match)
|
||||
device(2 2 match)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,83 @@
|
|||
* Extracted by KLayout
|
||||
|
||||
* cell RINGO
|
||||
* pin FB
|
||||
* pin VDD
|
||||
* pin OUT
|
||||
* pin ENABLE
|
||||
* pin VSS
|
||||
.SUBCKT RINGO 11 12 13 14 15
|
||||
* net 11 FB
|
||||
* net 12 VDD
|
||||
* net 13 OUT
|
||||
* net 14 ENABLE
|
||||
* net 15 VSS
|
||||
* cell instance $1 r0 *1 1.8,0
|
||||
X$1 12 1 15 12 11 14 15 ND2X1
|
||||
* cell instance $2 r0 *1 4.2,0
|
||||
X$2 12 2 15 12 1 15 INVX1
|
||||
* cell instance $3 r0 *1 6,0
|
||||
X$3 12 3 15 12 2 15 INVX1
|
||||
* cell instance $4 r0 *1 7.8,0
|
||||
X$4 12 4 15 12 3 15 INVX1
|
||||
* cell instance $5 r0 *1 9.6,0
|
||||
X$5 12 5 15 12 4 15 INVX1
|
||||
* cell instance $6 r0 *1 11.4,0
|
||||
X$6 12 6 15 12 5 15 INVX1
|
||||
* cell instance $7 r0 *1 13.2,0
|
||||
X$7 12 7 15 12 6 15 INVX1
|
||||
* cell instance $8 r0 *1 15,0
|
||||
X$8 12 8 15 12 7 15 INVX1
|
||||
* cell instance $9 r0 *1 16.8,0
|
||||
X$9 12 9 15 12 8 15 INVX1
|
||||
* cell instance $10 r0 *1 18.6,0
|
||||
X$10 12 10 15 12 9 15 INVX1
|
||||
* cell instance $11 r0 *1 20.4,0
|
||||
X$11 12 11 15 12 10 15 INVX1
|
||||
* cell instance $12 r0 *1 22.2,0
|
||||
X$12 12 13 15 12 11 15 INVX1
|
||||
.ENDS RINGO
|
||||
|
||||
* cell INVX1
|
||||
* pin VDD
|
||||
* pin OUT
|
||||
* pin VSS
|
||||
* pin
|
||||
* pin IN
|
||||
* pin SUBSTRATE
|
||||
.SUBCKT INVX1 1 2 3 4 5 6
|
||||
* net 1 VDD
|
||||
* net 2 OUT
|
||||
* net 3 VSS
|
||||
* net 5 IN
|
||||
* net 6 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.6375P PS=3.85U PD=3.85U
|
||||
* device instance $2 r0 *1 0.85,2.135 NMOS
|
||||
M$2 3 5 2 6 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.40375P PS=2.75U PD=2.75U
|
||||
.ENDS INVX1
|
||||
|
||||
* cell ND2X1
|
||||
* pin VDD
|
||||
* pin OUT
|
||||
* pin VSS
|
||||
* pin
|
||||
* pin B
|
||||
* pin A
|
||||
* pin SUBSTRATE
|
||||
.SUBCKT ND2X1 1 2 3 4 5 6 7
|
||||
* net 1 VDD
|
||||
* net 2 OUT
|
||||
* net 3 VSS
|
||||
* net 5 B
|
||||
* net 6 A
|
||||
* net 7 SUBSTRATE
|
||||
* device instance $1 r0 *1 0.85,5.8 PMOS
|
||||
M$1 2 6 1 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
|
||||
* device instance $2 r0 *1 1.55,5.8 PMOS
|
||||
M$2 1 5 2 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
|
||||
* device instance $3 r0 *1 0.85,2.135 NMOS
|
||||
M$3 3 6 8 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
|
||||
* device instance $4 r0 *1 1.55,2.135 NMOS
|
||||
M$4 8 5 2 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
|
||||
.ENDS ND2X1
|
||||
|
|
@ -0,0 +1,79 @@
|
|||
|
||||
source($lvs_test_source, "RINGO")
|
||||
|
||||
report_lvs($lvs_test_target_lvsdb, true)
|
||||
|
||||
target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
|
||||
|
||||
schematic("ringo_off_target.cir")
|
||||
|
||||
tolerance("PMOS", "L", 0.001) # absolute
|
||||
tolerance("PMOS", "W", 0.01, 0.1) # relative + absolute
|
||||
tolerance("NMOS", "L", :absolute => 0.01)
|
||||
tolerance("NMOS", "W", :relative => 0.07)
|
||||
|
||||
deep
|
||||
|
||||
# Drawing layers
|
||||
|
||||
nwell = input(1, 0)
|
||||
active = input(2, 0)
|
||||
pplus = input(3, 0)
|
||||
nplus = input(4, 0)
|
||||
poly = input(5, 0)
|
||||
contact = input(8, 0)
|
||||
metal1 = input(9, 0)
|
||||
via1 = input(10, 0)
|
||||
metal2 = input(11, 0)
|
||||
|
||||
# Bulk layer for terminal provisioning
|
||||
|
||||
bulk = polygon_layer
|
||||
|
||||
# Computed layers
|
||||
|
||||
active_in_nwell = active & nwell
|
||||
pactive = active_in_nwell & pplus
|
||||
pgate = pactive & poly
|
||||
psd = pactive - pgate
|
||||
ntie = active_in_nwell & nplus
|
||||
|
||||
active_outside_nwell = active - nwell
|
||||
nactive = active_outside_nwell & nplus
|
||||
ngate = nactive & poly
|
||||
nsd = nactive - ngate
|
||||
ptie = active_outside_nwell & pplus
|
||||
|
||||
# Device extraction
|
||||
|
||||
# PMOS transistor device extraction
|
||||
extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
|
||||
"tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell })
|
||||
|
||||
# NMOS transistor device extraction
|
||||
extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
|
||||
"tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk })
|
||||
|
||||
# Define connectivity for netlist extraction
|
||||
|
||||
# Inter-layer
|
||||
connect(psd, contact)
|
||||
connect(nsd, contact)
|
||||
connect(poly, contact)
|
||||
connect(ntie, contact)
|
||||
connect(nwell, ntie)
|
||||
connect(ptie, contact)
|
||||
connect(contact, metal1)
|
||||
connect(metal1, via1)
|
||||
connect(via1, metal2)
|
||||
|
||||
# Global
|
||||
connect_global(bulk, "SUBSTRATE")
|
||||
connect_global(ptie, "SUBSTRATE")
|
||||
|
||||
# Compare section
|
||||
|
||||
netlist.simplify
|
||||
|
||||
compare
|
||||
|
||||
|
|
@ -0,0 +1,908 @@
|
|||
#%lvsdb-klayout
|
||||
|
||||
# Layout
|
||||
layout(
|
||||
top(RINGO)
|
||||
unit(0.001)
|
||||
|
||||
# Layer section
|
||||
# This section lists the mask layers (drawing or derived) and their connections.
|
||||
|
||||
# Mask layers
|
||||
layer(l3 '1/0')
|
||||
layer(l4 '5/0')
|
||||
layer(l8 '8/0')
|
||||
layer(l11 '9/0')
|
||||
layer(l12 '10/0')
|
||||
layer(l13 '11/0')
|
||||
layer(l7)
|
||||
layer(l2)
|
||||
layer(l9)
|
||||
layer(l6)
|
||||
layer(l10)
|
||||
|
||||
# Mask layer connectivity
|
||||
connect(l3 l3 l9)
|
||||
connect(l4 l4 l8)
|
||||
connect(l8 l4 l8 l11 l2 l9 l6 l10)
|
||||
connect(l11 l8 l11 l12)
|
||||
connect(l12 l11 l12 l13)
|
||||
connect(l13 l12 l13)
|
||||
connect(l7 l7)
|
||||
connect(l2 l8 l2)
|
||||
connect(l9 l3 l8 l9)
|
||||
connect(l6 l8 l6)
|
||||
connect(l10 l8 l10)
|
||||
|
||||
# Global nets and connectivity
|
||||
global(l7 SUBSTRATE)
|
||||
global(l10 SUBSTRATE)
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Device abstracts section
|
||||
# Device abstracts list the pin shapes of the devices.
|
||||
device(D$PMOS PMOS
|
||||
terminal(S
|
||||
rect(l2 (-550 -750) (425 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l2 (125 -750) (450 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$PMOS$1 PMOS
|
||||
terminal(S
|
||||
rect(l2 (-575 -750) (450 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l2 (125 -750) (425 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$PMOS$2 PMOS
|
||||
terminal(S
|
||||
rect(l2 (-550 -750) (425 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l2 (125 -750) (425 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$NMOS NMOS
|
||||
terminal(S
|
||||
rect(l6 (-550 -475) (425 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l6 (125 -475) (450 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
device(D$NMOS$1 NMOS
|
||||
terminal(S
|
||||
rect(l6 (-575 -475) (450 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l6 (125 -475) (425 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
device(D$NMOS$2 NMOS
|
||||
terminal(S
|
||||
rect(l6 (-550 -475) (425 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l6 (125 -475) (425 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(ND2X1
|
||||
|
||||
# Circuit boundary
|
||||
rect((-100 400) (2600 7600))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(VDD)
|
||||
rect(l8 (1110 5160) (180 180))
|
||||
rect(l8 (-180 920) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l11 (-240 -790) (300 1700))
|
||||
rect(l11 (-1350 0) (2400 800))
|
||||
rect(l11 (-1151 -401) (2 2))
|
||||
rect(l2 (-276 -2151) (425 1500))
|
||||
rect(l2 (-400 -1500) (425 1500))
|
||||
)
|
||||
net(2 name(OUT)
|
||||
rect(l8 (1810 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-1580 3760) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (1220 920) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
|
||||
rect(l11 (-110 1390) (300 1400))
|
||||
polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
|
||||
rect(l11 (-141 -501) (2 2))
|
||||
rect(l11 (-1751 1099) (300 1400))
|
||||
rect(l11 (1100 -1700) (300 300))
|
||||
rect(l11 (-300 0) (300 1400))
|
||||
rect(l2 (-1750 -1450) (425 1500))
|
||||
rect(l2 (950 -1500) (425 1500))
|
||||
rect(l6 (-425 -4890) (425 950))
|
||||
)
|
||||
net(3 name(VSS)
|
||||
rect(l8 (410 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -1300) (300 1360))
|
||||
rect(l11 (-650 -2160) (2400 800))
|
||||
rect(l11 (-1151 -401) (2 2))
|
||||
rect(l6 (-951 859) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l3 (-100 4500) (2600 3500))
|
||||
)
|
||||
net(5 name(B)
|
||||
rect(l4 (1425 2860) (250 1940))
|
||||
rect(l4 (-345 -950) (300 300))
|
||||
rect(l4 (-205 650) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-285 1050) (180 180))
|
||||
rect(l11 (-71 -91) (2 2))
|
||||
rect(l11 (-171 -151) (300 300))
|
||||
)
|
||||
net(6 name(A)
|
||||
rect(l4 (725 2860) (250 1940))
|
||||
rect(l4 (-325 -1850) (300 300))
|
||||
rect(l4 (-225 1550) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-265 150) (180 180))
|
||||
rect(l11 (-91 -91) (2 2))
|
||||
rect(l11 (-151 -151) (300 300))
|
||||
)
|
||||
net(7 name(SUBSTRATE))
|
||||
net(8
|
||||
rect(l6 (975 1660) (425 950))
|
||||
rect(l6 (-400 -950) (425 950))
|
||||
)
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4)
|
||||
pin(5 name(B))
|
||||
pin(6 name(A))
|
||||
pin(7 name(SUBSTRATE))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 D$PMOS
|
||||
location(850 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.6375)
|
||||
param(AD 0.3375)
|
||||
param(PS 3.85)
|
||||
param(PD 1.95)
|
||||
terminal(S 2)
|
||||
terminal(G 6)
|
||||
terminal(D 1)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 D$PMOS$1
|
||||
location(1550 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.3375)
|
||||
param(AD 0.6375)
|
||||
param(PS 1.95)
|
||||
param(PD 3.85)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(3 D$NMOS
|
||||
location(850 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.40375)
|
||||
param(AD 0.21375)
|
||||
param(PS 2.75)
|
||||
param(PD 1.4)
|
||||
terminal(S 3)
|
||||
terminal(G 6)
|
||||
terminal(D 8)
|
||||
terminal(B 7)
|
||||
)
|
||||
device(4 D$NMOS$1
|
||||
location(1550 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.21375)
|
||||
param(AD 0.40375)
|
||||
param(PS 1.4)
|
||||
param(PD 2.75)
|
||||
terminal(S 8)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 7)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(INVX1
|
||||
|
||||
# Circuit boundary
|
||||
rect((-100 400) (2000 7600))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(VDD)
|
||||
rect(l8 (410 6260) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l11 (-240 -240) (300 1400))
|
||||
rect(l11 (-650 300) (1800 800))
|
||||
rect(l11 (-1450 -1100) (300 300))
|
||||
rect(l11 (299 399) (2 2))
|
||||
rect(l2 (-651 -2151) (425 1500))
|
||||
)
|
||||
net(2 name(OUT)
|
||||
rect(l8 (1110 5160) (180 180))
|
||||
rect(l8 (-180 920) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -4120) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -790) (300 4790))
|
||||
rect(l11 (-151 -2501) (2 2))
|
||||
rect(l2 (-226 1049) (425 1500))
|
||||
rect(l6 (-425 -4890) (425 950))
|
||||
)
|
||||
net(3 name(VSS)
|
||||
rect(l8 (410 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -1300) (300 1360))
|
||||
rect(l11 (-650 -2160) (1800 800))
|
||||
rect(l11 (-851 -401) (2 2))
|
||||
rect(l6 (-651 859) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l3 (-100 4500) (2000 3500))
|
||||
)
|
||||
net(5 name(IN)
|
||||
rect(l4 (725 2860) (250 1940))
|
||||
rect(l4 (-525 -1850) (300 300))
|
||||
rect(l4 (-25 1550) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-465 150) (180 180))
|
||||
rect(l11 (-91 -91) (2 2))
|
||||
rect(l11 (-151 -151) (300 300))
|
||||
)
|
||||
net(6 name(SUBSTRATE))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4)
|
||||
pin(5 name(IN))
|
||||
pin(6 name(SUBSTRATE))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 D$PMOS$2
|
||||
location(850 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.6375)
|
||||
param(AD 0.6375)
|
||||
param(PS 3.85)
|
||||
param(PD 3.85)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 D$NMOS$2
|
||||
location(850 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.40375)
|
||||
param(AD 0.40375)
|
||||
param(PS 2.75)
|
||||
param(PD 2.75)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Circuit boundary
|
||||
rect((0 350) (25800 7650))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1
|
||||
rect(l11 (4040 2950) (610 300))
|
||||
)
|
||||
net(2
|
||||
rect(l11 (5550 2950) (900 300))
|
||||
)
|
||||
net(3
|
||||
rect(l11 (7350 2950) (900 300))
|
||||
)
|
||||
net(4
|
||||
rect(l11 (9150 2950) (900 300))
|
||||
)
|
||||
net(5
|
||||
rect(l11 (10950 2950) (900 300))
|
||||
)
|
||||
net(6
|
||||
rect(l11 (12750 2950) (900 300))
|
||||
)
|
||||
net(7
|
||||
rect(l11 (14550 2950) (900 300))
|
||||
)
|
||||
net(8
|
||||
rect(l11 (16350 2950) (900 300))
|
||||
)
|
||||
net(9
|
||||
rect(l11 (18150 2950) (900 300))
|
||||
)
|
||||
net(10
|
||||
rect(l11 (19950 2950) (900 300))
|
||||
)
|
||||
net(11 name(FB)
|
||||
rect(l11 (21750 2950) (900 300))
|
||||
rect(l11 (-19530 590) (320 320))
|
||||
rect(l11 (17820 -320) (320 320))
|
||||
rect(l12 (-18400 -260) (200 200))
|
||||
rect(l12 (17940 -200) (200 200))
|
||||
rect(l13 (-18040 -300) (17740 400))
|
||||
rect(l13 (-17921 -201) (2 2))
|
||||
rect(l13 (-221 -201) (400 400))
|
||||
rect(l13 (17740 -400) (400 400))
|
||||
)
|
||||
net(12 name(VDD)
|
||||
rect(l3 (500 4500) (1400 3500))
|
||||
rect(l3 (-1900 -3500) (600 3500))
|
||||
rect(l3 (23300 -3500) (1400 3500))
|
||||
rect(l3 (-100 -3500) (600 3500))
|
||||
rect(l8 (-24690 -1240) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (23220 370) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l11 (-21741 859) (2 2))
|
||||
rect(l11 (-2351 -451) (1200 800))
|
||||
rect(l11 (-750 -1450) (300 1400))
|
||||
rect(l11 (-101 -351) (2 2))
|
||||
rect(l11 (-1251 -401) (600 800))
|
||||
rect(l11 (23400 -800) (1200 800))
|
||||
rect(l11 (-750 -1450) (300 1400))
|
||||
rect(l11 (-101 -351) (2 2))
|
||||
rect(l11 (549 -401) (600 800))
|
||||
rect(l9 (-24850 -1500) (500 1500))
|
||||
rect(l9 (22900 -1500) (500 1500))
|
||||
)
|
||||
net(13 name(OUT)
|
||||
rect(l11 (23440 3840) (320 320))
|
||||
rect(l12 (-260 -260) (200 200))
|
||||
rect(l13 (-101 -101) (2 2))
|
||||
rect(l13 (-201 -201) (400 400))
|
||||
)
|
||||
net(14 name(ENABLE)
|
||||
rect(l11 (2440 2940) (320 320))
|
||||
rect(l12 (-260 -260) (200 200))
|
||||
rect(l13 (-101 -101) (2 2))
|
||||
rect(l13 (-201 -201) (400 400))
|
||||
)
|
||||
net(15 name(VSS)
|
||||
rect(l8 (1110 1610) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (23220 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-21741 -391) (2 2))
|
||||
rect(l11 (-1901 -401) (300 1400))
|
||||
rect(l11 (-750 -1450) (1200 800))
|
||||
rect(l11 (-551 -401) (2 2))
|
||||
rect(l11 (-1251 -401) (600 800))
|
||||
rect(l11 (23850 -750) (300 1400))
|
||||
rect(l11 (-750 -1450) (1200 800))
|
||||
rect(l11 (-551 -401) (2 2))
|
||||
rect(l11 (549 -401) (600 800))
|
||||
rect(l10 (-24850 -800) (500 1500))
|
||||
rect(l10 (22900 -1500) (500 1500))
|
||||
)
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(11 name(FB))
|
||||
pin(12 name(VDD))
|
||||
pin(13 name(OUT))
|
||||
pin(14 name(ENABLE))
|
||||
pin(15 name(VSS))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 ND2X1 location(1800 0)
|
||||
pin(0 12)
|
||||
pin(1 1)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 11)
|
||||
pin(5 14)
|
||||
pin(6 15)
|
||||
)
|
||||
circuit(2 INVX1 location(4200 0)
|
||||
pin(0 12)
|
||||
pin(1 2)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 1)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(3 INVX1 location(6000 0)
|
||||
pin(0 12)
|
||||
pin(1 3)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 2)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(4 INVX1 location(7800 0)
|
||||
pin(0 12)
|
||||
pin(1 4)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 3)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(5 INVX1 location(9600 0)
|
||||
pin(0 12)
|
||||
pin(1 5)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 4)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(6 INVX1 location(11400 0)
|
||||
pin(0 12)
|
||||
pin(1 6)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 5)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(7 INVX1 location(13200 0)
|
||||
pin(0 12)
|
||||
pin(1 7)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 6)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(8 INVX1 location(15000 0)
|
||||
pin(0 12)
|
||||
pin(1 8)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 7)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(9 INVX1 location(16800 0)
|
||||
pin(0 12)
|
||||
pin(1 9)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 8)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(10 INVX1 location(18600 0)
|
||||
pin(0 12)
|
||||
pin(1 10)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 9)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(11 INVX1 location(20400 0)
|
||||
pin(0 12)
|
||||
pin(1 11)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 10)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(12 INVX1 location(22200 0)
|
||||
pin(0 12)
|
||||
pin(1 13)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 11)
|
||||
pin(5 15)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Reference netlist
|
||||
reference(
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(ND2X1
|
||||
|
||||
# Nets
|
||||
net(1 name(VDD))
|
||||
net(2 name(OUT))
|
||||
net(3 name(VSS))
|
||||
net(4 name(NWELL))
|
||||
net(5 name(B))
|
||||
net(6 name(A))
|
||||
net(7 name(BULK))
|
||||
net(8 name('1'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4 name(NWELL))
|
||||
pin(5 name(B))
|
||||
pin(6 name(A))
|
||||
pin(7 name(BULK))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name($1)
|
||||
param(L 0.251)
|
||||
param(W 1.6)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(G 6)
|
||||
terminal(D 1)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 PMOS
|
||||
name($2)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(3 NMOS
|
||||
name($3)
|
||||
param(L 0.26)
|
||||
param(W 1)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 3)
|
||||
terminal(G 6)
|
||||
terminal(D 8)
|
||||
terminal(B 7)
|
||||
)
|
||||
device(4 NMOS
|
||||
name($4)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 8)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 7)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(INVX1
|
||||
|
||||
# Nets
|
||||
net(1 name(VDD))
|
||||
net(2 name(OUT))
|
||||
net(3 name(VSS))
|
||||
net(4 name(NWELL))
|
||||
net(5 name(IN))
|
||||
net(6 name(BULK))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4 name(NWELL))
|
||||
pin(5 name(IN))
|
||||
pin(6 name(BULK))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name($1)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 NMOS
|
||||
name($2)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Nets
|
||||
net(1 name(VSS))
|
||||
net(2 name(VDD))
|
||||
net(3 name(FB))
|
||||
net(4 name(ENABLE))
|
||||
net(5 name(OUT))
|
||||
net(6 name('1'))
|
||||
net(7 name('2'))
|
||||
net(8 name('3'))
|
||||
net(9 name('4'))
|
||||
net(10 name('5'))
|
||||
net(11 name('6'))
|
||||
net(12 name('7'))
|
||||
net(13 name('8'))
|
||||
net(14 name('9'))
|
||||
net(15 name('10'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VSS))
|
||||
pin(2 name(VDD))
|
||||
pin(3 name(FB))
|
||||
pin(4 name(ENABLE))
|
||||
pin(5 name(OUT))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 ND2X1 name($1)
|
||||
pin(0 2)
|
||||
pin(1 6)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 3)
|
||||
pin(5 4)
|
||||
pin(6 1)
|
||||
)
|
||||
circuit(2 INVX1 name($2)
|
||||
pin(0 2)
|
||||
pin(1 7)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 6)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(3 INVX1 name($3)
|
||||
pin(0 2)
|
||||
pin(1 8)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 7)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(4 INVX1 name($4)
|
||||
pin(0 2)
|
||||
pin(1 9)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 8)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(5 INVX1 name($5)
|
||||
pin(0 2)
|
||||
pin(1 10)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 9)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(6 INVX1 name($6)
|
||||
pin(0 2)
|
||||
pin(1 11)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 10)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(7 INVX1 name($7)
|
||||
pin(0 2)
|
||||
pin(1 12)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 11)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(8 INVX1 name($8)
|
||||
pin(0 2)
|
||||
pin(1 13)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 12)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(9 INVX1 name($9)
|
||||
pin(0 2)
|
||||
pin(1 14)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 13)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(10 INVX1 name($10)
|
||||
pin(0 2)
|
||||
pin(1 15)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 14)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(11 INVX1 name($11)
|
||||
pin(0 2)
|
||||
pin(1 3)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 15)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(12 INVX1 name($12)
|
||||
pin(0 2)
|
||||
pin(1 5)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 3)
|
||||
pin(5 1)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Cross reference
|
||||
xref(
|
||||
circuit(INVX1 INVX1 match
|
||||
xref(
|
||||
net(4 4 match)
|
||||
net(5 5 match)
|
||||
net(2 2 match)
|
||||
net(6 6 match)
|
||||
net(1 1 match)
|
||||
net(3 3 match)
|
||||
pin(3 3 match)
|
||||
pin(4 4 match)
|
||||
pin(1 1 match)
|
||||
pin(5 5 match)
|
||||
pin(0 0 match)
|
||||
pin(2 2 match)
|
||||
device(2 2 match)
|
||||
device(1 1 match)
|
||||
)
|
||||
)
|
||||
circuit(ND2X1 ND2X1 match
|
||||
xref(
|
||||
net(8 8 match)
|
||||
net(4 4 match)
|
||||
net(6 6 match)
|
||||
net(5 5 match)
|
||||
net(2 2 match)
|
||||
net(7 7 match)
|
||||
net(1 1 match)
|
||||
net(3 3 match)
|
||||
pin(3 3 match)
|
||||
pin(5 5 match)
|
||||
pin(4 4 match)
|
||||
pin(1 1 match)
|
||||
pin(6 6 match)
|
||||
pin(0 0 match)
|
||||
pin(2 2 match)
|
||||
device(3 3 match)
|
||||
device(4 4 match)
|
||||
device(1 1 match)
|
||||
device(2 2 match)
|
||||
)
|
||||
)
|
||||
circuit(RINGO RINGO match
|
||||
xref(
|
||||
net(1 6 match)
|
||||
net(10 15 match)
|
||||
net(2 7 match)
|
||||
net(3 8 match)
|
||||
net(4 9 match)
|
||||
net(5 10 match)
|
||||
net(6 11 match)
|
||||
net(7 12 match)
|
||||
net(8 13 match)
|
||||
net(9 14 match)
|
||||
net(14 4 match)
|
||||
net(11 3 match)
|
||||
net(13 5 match)
|
||||
net(12 2 match)
|
||||
net(15 1 match)
|
||||
pin(3 3 match)
|
||||
pin(0 2 match)
|
||||
pin(2 4 match)
|
||||
pin(1 1 match)
|
||||
pin(4 0 match)
|
||||
circuit(2 2 match)
|
||||
circuit(3 3 match)
|
||||
circuit(4 4 match)
|
||||
circuit(5 5 match)
|
||||
circuit(6 6 match)
|
||||
circuit(7 7 match)
|
||||
circuit(8 8 match)
|
||||
circuit(9 9 match)
|
||||
circuit(10 10 match)
|
||||
circuit(11 11 match)
|
||||
circuit(12 12 match)
|
||||
circuit(1 1 match)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,908 @@
|
|||
#%lvsdb-klayout
|
||||
|
||||
# Layout
|
||||
layout(
|
||||
top(RINGO)
|
||||
unit(0.001)
|
||||
|
||||
# Layer section
|
||||
# This section lists the mask layers (drawing or derived) and their connections.
|
||||
|
||||
# Mask layers
|
||||
layer(l3 '1/0')
|
||||
layer(l4 '5/0')
|
||||
layer(l8 '8/0')
|
||||
layer(l11 '9/0')
|
||||
layer(l12 '10/0')
|
||||
layer(l13 '11/0')
|
||||
layer(l7)
|
||||
layer(l2)
|
||||
layer(l9)
|
||||
layer(l6)
|
||||
layer(l10)
|
||||
|
||||
# Mask layer connectivity
|
||||
connect(l3 l3 l9)
|
||||
connect(l4 l4 l8)
|
||||
connect(l8 l4 l8 l11 l2 l9 l6 l10)
|
||||
connect(l11 l8 l11 l12)
|
||||
connect(l12 l11 l12 l13)
|
||||
connect(l13 l12 l13)
|
||||
connect(l7 l7)
|
||||
connect(l2 l8 l2)
|
||||
connect(l9 l3 l8 l9)
|
||||
connect(l6 l8 l6)
|
||||
connect(l10 l8 l10)
|
||||
|
||||
# Global nets and connectivity
|
||||
global(l7 SUBSTRATE)
|
||||
global(l10 SUBSTRATE)
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Device abstracts section
|
||||
# Device abstracts list the pin shapes of the devices.
|
||||
device(D$PMOS PMOS
|
||||
terminal(S
|
||||
rect(l2 (-550 -750) (425 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l2 (125 -750) (450 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$PMOS$1 PMOS
|
||||
terminal(S
|
||||
rect(l2 (-575 -750) (450 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l2 (125 -750) (425 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$PMOS$2 PMOS
|
||||
terminal(S
|
||||
rect(l2 (-550 -750) (425 1500))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -750) (250 1500))
|
||||
)
|
||||
terminal(D
|
||||
rect(l2 (125 -750) (425 1500))
|
||||
)
|
||||
terminal(B
|
||||
rect(l3 (-125 -750) (250 1500))
|
||||
)
|
||||
)
|
||||
device(D$NMOS NMOS
|
||||
terminal(S
|
||||
rect(l6 (-550 -475) (425 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l6 (125 -475) (450 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
device(D$NMOS$1 NMOS
|
||||
terminal(S
|
||||
rect(l6 (-575 -475) (450 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l6 (125 -475) (425 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
device(D$NMOS$2 NMOS
|
||||
terminal(S
|
||||
rect(l6 (-550 -475) (425 950))
|
||||
)
|
||||
terminal(G
|
||||
rect(l4 (-125 -475) (250 950))
|
||||
)
|
||||
terminal(D
|
||||
rect(l6 (125 -475) (425 950))
|
||||
)
|
||||
terminal(B
|
||||
rect(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(ND2X1
|
||||
|
||||
# Circuit boundary
|
||||
rect((-100 400) (2600 7600))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(VDD)
|
||||
rect(l8 (1110 5160) (180 180))
|
||||
rect(l8 (-180 920) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l11 (-240 -790) (300 1700))
|
||||
rect(l11 (-1350 0) (2400 800))
|
||||
rect(l11 (-1151 -401) (2 2))
|
||||
rect(l2 (-276 -2151) (425 1500))
|
||||
rect(l2 (-400 -1500) (425 1500))
|
||||
)
|
||||
net(2 name(OUT)
|
||||
rect(l8 (1810 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-1580 3760) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (1220 920) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
|
||||
rect(l11 (-110 1390) (300 1400))
|
||||
polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
|
||||
rect(l11 (-141 -501) (2 2))
|
||||
rect(l11 (-1751 1099) (300 1400))
|
||||
rect(l11 (1100 -1700) (300 300))
|
||||
rect(l11 (-300 0) (300 1400))
|
||||
rect(l2 (-375 -1450) (425 1500))
|
||||
rect(l2 (-1800 -1500) (425 1500))
|
||||
rect(l6 (950 -4890) (425 950))
|
||||
)
|
||||
net(3 name(VSS)
|
||||
rect(l8 (410 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -1300) (300 1360))
|
||||
rect(l11 (-650 -2160) (2400 800))
|
||||
rect(l11 (-1151 -401) (2 2))
|
||||
rect(l6 (-951 859) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l3 (-100 4500) (2600 3500))
|
||||
)
|
||||
net(5 name(B)
|
||||
rect(l4 (1425 2860) (250 1940))
|
||||
rect(l4 (-345 -950) (300 300))
|
||||
rect(l4 (-205 650) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-285 1050) (180 180))
|
||||
rect(l11 (-71 -91) (2 2))
|
||||
rect(l11 (-171 -151) (300 300))
|
||||
)
|
||||
net(6 name(A)
|
||||
rect(l4 (725 2860) (250 1940))
|
||||
rect(l4 (-325 -1850) (300 300))
|
||||
rect(l4 (-225 1550) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-265 150) (180 180))
|
||||
rect(l11 (-91 -91) (2 2))
|
||||
rect(l11 (-151 -151) (300 300))
|
||||
)
|
||||
net(7 name(SUBSTRATE))
|
||||
net(8
|
||||
rect(l6 (975 1660) (425 950))
|
||||
rect(l6 (-400 -950) (425 950))
|
||||
)
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4)
|
||||
pin(5 name(B))
|
||||
pin(6 name(A))
|
||||
pin(7 name(SUBSTRATE))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 D$PMOS
|
||||
location(850 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.6375)
|
||||
param(AD 0.3375)
|
||||
param(PS 3.85)
|
||||
param(PD 1.95)
|
||||
terminal(S 2)
|
||||
terminal(G 6)
|
||||
terminal(D 1)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 D$PMOS$1
|
||||
location(1550 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.3375)
|
||||
param(AD 0.6375)
|
||||
param(PS 1.95)
|
||||
param(PD 3.85)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(3 D$NMOS
|
||||
location(850 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.40375)
|
||||
param(AD 0.21375)
|
||||
param(PS 2.75)
|
||||
param(PD 1.4)
|
||||
terminal(S 3)
|
||||
terminal(G 6)
|
||||
terminal(D 8)
|
||||
terminal(B 7)
|
||||
)
|
||||
device(4 D$NMOS$1
|
||||
location(1550 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.21375)
|
||||
param(AD 0.40375)
|
||||
param(PS 1.4)
|
||||
param(PD 2.75)
|
||||
terminal(S 8)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 7)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(INVX1
|
||||
|
||||
# Circuit boundary
|
||||
rect((-100 400) (2000 7600))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1 name(VDD)
|
||||
rect(l8 (410 6260) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l11 (-240 -240) (300 1400))
|
||||
rect(l11 (-650 300) (1800 800))
|
||||
rect(l11 (-1450 -1100) (300 300))
|
||||
rect(l11 (299 399) (2 2))
|
||||
rect(l2 (-651 -2151) (425 1500))
|
||||
)
|
||||
net(2 name(OUT)
|
||||
rect(l8 (1110 5160) (180 180))
|
||||
rect(l8 (-180 920) (180 180))
|
||||
rect(l8 (-180 -730) (180 180))
|
||||
rect(l8 (-180 -4120) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -790) (300 4790))
|
||||
rect(l11 (-151 -2501) (2 2))
|
||||
rect(l2 (-226 1049) (425 1500))
|
||||
rect(l6 (-425 -4890) (425 950))
|
||||
)
|
||||
net(3 name(VSS)
|
||||
rect(l8 (410 1770) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-240 -1300) (300 1360))
|
||||
rect(l11 (-650 -2160) (1800 800))
|
||||
rect(l11 (-851 -401) (2 2))
|
||||
rect(l6 (-651 859) (425 950))
|
||||
)
|
||||
net(4
|
||||
rect(l3 (-100 4500) (2000 3500))
|
||||
)
|
||||
net(5 name(IN)
|
||||
rect(l4 (725 2860) (250 1940))
|
||||
rect(l4 (-525 -1850) (300 300))
|
||||
rect(l4 (-25 1550) (250 2000))
|
||||
rect(l4 (-250 -2000) (250 2000))
|
||||
rect(l4 (-250 -5390) (250 1450))
|
||||
rect(l8 (-465 150) (180 180))
|
||||
rect(l11 (-91 -91) (2 2))
|
||||
rect(l11 (-151 -151) (300 300))
|
||||
)
|
||||
net(6 name(SUBSTRATE))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4)
|
||||
pin(5 name(IN))
|
||||
pin(6 name(SUBSTRATE))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 D$PMOS$2
|
||||
location(850 5800)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0.6375)
|
||||
param(AD 0.6375)
|
||||
param(PS 3.85)
|
||||
param(PD 3.85)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 D$NMOS$2
|
||||
location(850 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.40375)
|
||||
param(AD 0.40375)
|
||||
param(PS 2.75)
|
||||
param(PD 2.75)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Circuit boundary
|
||||
rect((0 350) (25800 7650))
|
||||
|
||||
# Nets with their geometries
|
||||
net(1
|
||||
rect(l11 (4040 2950) (610 300))
|
||||
)
|
||||
net(2
|
||||
rect(l11 (5550 2950) (900 300))
|
||||
)
|
||||
net(3
|
||||
rect(l11 (7350 2950) (900 300))
|
||||
)
|
||||
net(4
|
||||
rect(l11 (9150 2950) (900 300))
|
||||
)
|
||||
net(5
|
||||
rect(l11 (10950 2950) (900 300))
|
||||
)
|
||||
net(6
|
||||
rect(l11 (12750 2950) (900 300))
|
||||
)
|
||||
net(7
|
||||
rect(l11 (14550 2950) (900 300))
|
||||
)
|
||||
net(8
|
||||
rect(l11 (16350 2950) (900 300))
|
||||
)
|
||||
net(9
|
||||
rect(l11 (18150 2950) (900 300))
|
||||
)
|
||||
net(10
|
||||
rect(l11 (19950 2950) (900 300))
|
||||
)
|
||||
net(11 name(FB)
|
||||
rect(l11 (21750 2950) (900 300))
|
||||
rect(l11 (-19530 590) (320 320))
|
||||
rect(l11 (17820 -320) (320 320))
|
||||
rect(l12 (-18400 -260) (200 200))
|
||||
rect(l12 (17940 -200) (200 200))
|
||||
rect(l13 (-18040 -300) (17740 400))
|
||||
rect(l13 (-17921 -201) (2 2))
|
||||
rect(l13 (-221 -201) (400 400))
|
||||
rect(l13 (17740 -400) (400 400))
|
||||
)
|
||||
net(12 name(VDD)
|
||||
rect(l3 (500 4500) (1400 3500))
|
||||
rect(l3 (-1900 -3500) (600 3500))
|
||||
rect(l3 (23300 -3500) (1400 3500))
|
||||
rect(l3 (-100 -3500) (600 3500))
|
||||
rect(l8 (-24690 -1240) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (23220 370) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l11 (-21741 859) (2 2))
|
||||
rect(l11 (-2351 -451) (1200 800))
|
||||
rect(l11 (-750 -1450) (300 1400))
|
||||
rect(l11 (-101 -351) (2 2))
|
||||
rect(l11 (-1251 -401) (600 800))
|
||||
rect(l11 (23400 -800) (1200 800))
|
||||
rect(l11 (-750 -1450) (300 1400))
|
||||
rect(l11 (-101 -351) (2 2))
|
||||
rect(l11 (549 -401) (600 800))
|
||||
rect(l9 (-24850 -1500) (500 1500))
|
||||
rect(l9 (22900 -1500) (500 1500))
|
||||
)
|
||||
net(13 name(OUT)
|
||||
rect(l11 (23440 3840) (320 320))
|
||||
rect(l12 (-260 -260) (200 200))
|
||||
rect(l13 (-101 -101) (2 2))
|
||||
rect(l13 (-201 -201) (400 400))
|
||||
)
|
||||
net(14 name(ENABLE)
|
||||
rect(l11 (2440 2940) (320 320))
|
||||
rect(l12 (-260 -260) (200 200))
|
||||
rect(l13 (-101 -101) (2 2))
|
||||
rect(l13 (-201 -201) (400 400))
|
||||
)
|
||||
net(15 name(VSS)
|
||||
rect(l8 (1110 1610) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l8 (23220 370) (180 180))
|
||||
rect(l8 (-180 -1280) (180 180))
|
||||
rect(l8 (-180 370) (180 180))
|
||||
rect(l11 (-21741 -391) (2 2))
|
||||
rect(l11 (-1901 -401) (300 1400))
|
||||
rect(l11 (-750 -1450) (1200 800))
|
||||
rect(l11 (-551 -401) (2 2))
|
||||
rect(l11 (-1251 -401) (600 800))
|
||||
rect(l11 (23850 -750) (300 1400))
|
||||
rect(l11 (-750 -1450) (1200 800))
|
||||
rect(l11 (-551 -401) (2 2))
|
||||
rect(l11 (549 -401) (600 800))
|
||||
rect(l10 (-24850 -800) (500 1500))
|
||||
rect(l10 (22900 -1500) (500 1500))
|
||||
)
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(11 name(FB))
|
||||
pin(12 name(VDD))
|
||||
pin(13 name(OUT))
|
||||
pin(14 name(ENABLE))
|
||||
pin(15 name(VSS))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 ND2X1 location(1800 0)
|
||||
pin(0 12)
|
||||
pin(1 1)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 11)
|
||||
pin(5 14)
|
||||
pin(6 15)
|
||||
)
|
||||
circuit(2 INVX1 location(4200 0)
|
||||
pin(0 12)
|
||||
pin(1 2)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 1)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(3 INVX1 location(6000 0)
|
||||
pin(0 12)
|
||||
pin(1 3)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 2)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(4 INVX1 location(7800 0)
|
||||
pin(0 12)
|
||||
pin(1 4)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 3)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(5 INVX1 location(9600 0)
|
||||
pin(0 12)
|
||||
pin(1 5)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 4)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(6 INVX1 location(11400 0)
|
||||
pin(0 12)
|
||||
pin(1 6)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 5)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(7 INVX1 location(13200 0)
|
||||
pin(0 12)
|
||||
pin(1 7)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 6)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(8 INVX1 location(15000 0)
|
||||
pin(0 12)
|
||||
pin(1 8)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 7)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(9 INVX1 location(16800 0)
|
||||
pin(0 12)
|
||||
pin(1 9)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 8)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(10 INVX1 location(18600 0)
|
||||
pin(0 12)
|
||||
pin(1 10)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 9)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(11 INVX1 location(20400 0)
|
||||
pin(0 12)
|
||||
pin(1 11)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 10)
|
||||
pin(5 15)
|
||||
)
|
||||
circuit(12 INVX1 location(22200 0)
|
||||
pin(0 12)
|
||||
pin(1 13)
|
||||
pin(2 15)
|
||||
pin(3 12)
|
||||
pin(4 11)
|
||||
pin(5 15)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Reference netlist
|
||||
reference(
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(ND2X1
|
||||
|
||||
# Nets
|
||||
net(1 name(VDD))
|
||||
net(2 name(OUT))
|
||||
net(3 name(VSS))
|
||||
net(4 name(NWELL))
|
||||
net(5 name(B))
|
||||
net(6 name(A))
|
||||
net(7 name(BULK))
|
||||
net(8 name('1'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4 name(NWELL))
|
||||
pin(5 name(B))
|
||||
pin(6 name(A))
|
||||
pin(7 name(BULK))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name($1)
|
||||
param(L 0.251)
|
||||
param(W 1.6)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 2)
|
||||
terminal(G 6)
|
||||
terminal(D 1)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 PMOS
|
||||
name($2)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(3 NMOS
|
||||
name($3)
|
||||
param(L 0.26)
|
||||
param(W 1)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 3)
|
||||
terminal(G 6)
|
||||
terminal(D 8)
|
||||
terminal(B 7)
|
||||
)
|
||||
device(4 NMOS
|
||||
name($4)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 8)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 7)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(INVX1
|
||||
|
||||
# Nets
|
||||
net(1 name(VDD))
|
||||
net(2 name(OUT))
|
||||
net(3 name(VSS))
|
||||
net(4 name(NWELL))
|
||||
net(5 name(IN))
|
||||
net(6 name(BULK))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4 name(NWELL))
|
||||
pin(5 name(IN))
|
||||
pin(6 name(BULK))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name($1)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 NMOS
|
||||
name($2)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 3)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 6)
|
||||
)
|
||||
|
||||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Nets
|
||||
net(1 name(VSS))
|
||||
net(2 name(VDD))
|
||||
net(3 name(FB))
|
||||
net(4 name(ENABLE))
|
||||
net(5 name(OUT))
|
||||
net(6 name('1'))
|
||||
net(7 name('2'))
|
||||
net(8 name('3'))
|
||||
net(9 name('4'))
|
||||
net(10 name('5'))
|
||||
net(11 name('6'))
|
||||
net(12 name('7'))
|
||||
net(13 name('8'))
|
||||
net(14 name('9'))
|
||||
net(15 name('10'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VSS))
|
||||
pin(2 name(VDD))
|
||||
pin(3 name(FB))
|
||||
pin(4 name(ENABLE))
|
||||
pin(5 name(OUT))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 ND2X1 name($1)
|
||||
pin(0 2)
|
||||
pin(1 6)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 3)
|
||||
pin(5 4)
|
||||
pin(6 1)
|
||||
)
|
||||
circuit(2 INVX1 name($2)
|
||||
pin(0 2)
|
||||
pin(1 7)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 6)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(3 INVX1 name($3)
|
||||
pin(0 2)
|
||||
pin(1 8)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 7)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(4 INVX1 name($4)
|
||||
pin(0 2)
|
||||
pin(1 9)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 8)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(5 INVX1 name($5)
|
||||
pin(0 2)
|
||||
pin(1 10)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 9)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(6 INVX1 name($6)
|
||||
pin(0 2)
|
||||
pin(1 11)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 10)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(7 INVX1 name($7)
|
||||
pin(0 2)
|
||||
pin(1 12)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 11)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(8 INVX1 name($8)
|
||||
pin(0 2)
|
||||
pin(1 13)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 12)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(9 INVX1 name($9)
|
||||
pin(0 2)
|
||||
pin(1 14)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 13)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(10 INVX1 name($10)
|
||||
pin(0 2)
|
||||
pin(1 15)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 14)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(11 INVX1 name($11)
|
||||
pin(0 2)
|
||||
pin(1 3)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 15)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(12 INVX1 name($12)
|
||||
pin(0 2)
|
||||
pin(1 5)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 3)
|
||||
pin(5 1)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Cross reference
|
||||
xref(
|
||||
circuit(INVX1 INVX1 match
|
||||
xref(
|
||||
net(4 4 match)
|
||||
net(5 5 match)
|
||||
net(2 2 match)
|
||||
net(6 6 match)
|
||||
net(1 1 match)
|
||||
net(3 3 match)
|
||||
pin(3 3 match)
|
||||
pin(4 4 match)
|
||||
pin(1 1 match)
|
||||
pin(5 5 match)
|
||||
pin(0 0 match)
|
||||
pin(2 2 match)
|
||||
device(2 2 match)
|
||||
device(1 1 match)
|
||||
)
|
||||
)
|
||||
circuit(ND2X1 ND2X1 match
|
||||
xref(
|
||||
net(8 8 match)
|
||||
net(4 4 match)
|
||||
net(6 6 match)
|
||||
net(5 5 match)
|
||||
net(2 2 match)
|
||||
net(7 7 match)
|
||||
net(1 1 match)
|
||||
net(3 3 match)
|
||||
pin(3 3 match)
|
||||
pin(5 5 match)
|
||||
pin(4 4 match)
|
||||
pin(1 1 match)
|
||||
pin(6 6 match)
|
||||
pin(0 0 match)
|
||||
pin(2 2 match)
|
||||
device(3 3 match)
|
||||
device(4 4 match)
|
||||
device(1 1 match)
|
||||
device(2 2 match)
|
||||
)
|
||||
)
|
||||
circuit(RINGO RINGO match
|
||||
xref(
|
||||
net(1 6 match)
|
||||
net(10 15 match)
|
||||
net(2 7 match)
|
||||
net(3 8 match)
|
||||
net(4 9 match)
|
||||
net(5 10 match)
|
||||
net(6 11 match)
|
||||
net(7 12 match)
|
||||
net(8 13 match)
|
||||
net(9 14 match)
|
||||
net(14 4 match)
|
||||
net(11 3 match)
|
||||
net(13 5 match)
|
||||
net(12 2 match)
|
||||
net(15 1 match)
|
||||
pin(3 3 match)
|
||||
pin(0 2 match)
|
||||
pin(2 4 match)
|
||||
pin(1 1 match)
|
||||
pin(4 0 match)
|
||||
circuit(2 2 match)
|
||||
circuit(3 3 match)
|
||||
circuit(4 4 match)
|
||||
circuit(5 5 match)
|
||||
circuit(6 6 match)
|
||||
circuit(7 7 match)
|
||||
circuit(8 8 match)
|
||||
circuit(9 9 match)
|
||||
circuit(10 10 match)
|
||||
circuit(11 11 match)
|
||||
circuit(12 12 match)
|
||||
circuit(1 1 match)
|
||||
)
|
||||
)
|
||||
)
|
||||
Loading…
Reference in New Issue