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42 Commits

Author SHA1 Message Date
Matthias Koefferlein 7d4310d343 Updated copyright to 2021 2021-01-05 22:57:48 +01:00
Matthias Köfferlein 8cdb6187b8
Fixed issue #617 (constness problem in netlist) (#622) 2020-09-14 18:33:24 +02:00
Matthias Koefferlein 8adeaaf938 Checked add/remove methods for Netlist objects - to avoid script mistakes. 2020-07-05 19:02:43 +02:00
Matthias Koefferlein 076206074f Updated tests for CentOS 6 2020-02-27 23:46:02 +01:00
Matthias Koefferlein 3b31109367 Added GSI binding for join_symmetric_nets, added method to get circuits by name pattern. 2020-02-27 12:17:35 +01:00
Matthias Koefferlein b35429291e WIP: join_nets implemented, join_symmetric_nets: enhanced detection of symmetric nets. 2020-02-27 00:52:03 +01:00
Matthias Koefferlein b8c82c4f8b Updated copyright notice to 2020 2020-01-05 00:59:43 +01:00
Matthias Koefferlein d5506a176a WIP: first implementation - needs testing. 2019-11-23 01:20:22 +01:00
Matthias Koefferlein d060147713 Enhancements for the netlist object properties 
- more memory efficient (single pointer only)
- iterator for properties
- NetlistObject#property_keys in GSI
 2019-11-12 23:00:49 +01:00
Matthias Koefferlein 0ce06125ca Introducing netlist object properties. 2019-11-11 07:02:02 +01:00
Matthias Koefferlein 36ee1efe16 WIP: speedup LVS 'align' by flattening top-down 2019-10-21 22:14:36 +02:00
Matthias Koefferlein 60ed0cdc89 Updated test golden data (mainly: nets are not purged when there is a subcircuit pin on it) 2019-08-29 23:26:03 +02:00
Matthias Koefferlein 45cdefcf9a Provide strict mode for device classes, dmos3/dmos4 for LVS 2019-08-20 23:12:17 +02:00
Matthias Koefferlein cef96902ad Boundary for circuits, reverted automatic generation of global pins 
- global pins have been generated for device cells too and lead
  to implicit pins which may not be desired. The original problem
  was how to make abstract circuits comparable. This has to be
  solved differently.
- Circuit boundaries are good for displaying the boxes for
  abstract circuits
 2019-07-09 19:55:48 +02:00
Matthias Koefferlein 5ce8dd2684 WIP: added circuit blankout. 2019-07-06 19:50:20 +02:00
Matthias Koefferlein 46dafd50ea WIP: unit tests updated 2019-06-22 10:15:32 +02:00
Matthias Koefferlein 10667d8e35 Bugfixed last commit, fixed unit tests. 2019-05-29 00:51:42 +02:00
Matthias Koefferlein 0f0dd42b4d Refactoring and GSI binding for combined device interface. 2019-05-10 18:32:05 +02:00
Matthias Koefferlein eabf558186 netlist exaction: selective net joining with labels 
Now, a glob pattern can be used to identify the labels
which implicitly join nets. Also, net joining now
only happens on top level.
 2019-04-15 23:24:27 +02:00
Matthias Koefferlein df2bd5e80a Netlist: flatten subcircuits, circuits 2019-04-06 23:36:08 +02:00
Matthias Koefferlein d255617051 WIP: netlist compare - tests for device class equivalence mapping, added Netlist#device_class_by_name 2019-03-28 18:01:22 +01:00
Matthias Koefferlein 2d4f23abd1 Updated tests. 2019-03-19 00:08:47 +01:00
Matthias Koefferlein d4d7ea8022 Updated copyright. 2019-01-08 01:09:25 +01:00
Matthias Koefferlein c80e335cd6 WIP: global nets integration in cluster builder. 2019-01-07 02:08:59 +01:00
Matthias Koefferlein 64c2548ab8 WIP: first steps towards global nets. 2019-01-06 15:28:40 +01:00
Matthias Koefferlein eb435d5d85 WIP: refactoring - separated pins of net into outgoing and subcircuit. 2019-01-06 12:53:22 +01:00
Matthias Koefferlein f989a85642 WIP: introduced Circuit::is_external_net 2018-12-30 18:44:30 +01:00
Matthias Koefferlein a787204e77 WIP: connect and disconnect terminal by name in GSI 2018-12-30 13:28:11 +01:00
Matthias Koefferlein 293c6f496e WIP: more query functions for netlist classes (i.e. net by name, device by name etc.), some refactoring, GSI bindings, tests. 2018-12-30 13:00:03 +01:00
Matthias Koefferlein 45b35f3aae WIP: to_string for netlist, tests, some bugfixes on device combination. 2018-12-29 22:18:58 +01:00
Matthias Koefferlein d57ede441c WIP: netlist topology - children, parents, top-down and bottom-up iteration. 2018-12-29 00:48:28 +01:00
Matthias Koefferlein 2f48479838 WIP: a bit of simplification, renaming of methods, parents for subcircuits, devices. References for circuits pointing to subcircuits. 2018-12-28 22:51:11 +01:00
Matthias Koefferlein 8b2902c31b WIP: introduced expanded net name 2018-12-27 10:43:25 +01:00
Matthias Koefferlein f0f620b1cd WIP: added subcircuit IDs for easier referencing. 2018-12-27 01:58:34 +01:00
Matthias Koefferlein 2171b98bd8 WIP: introduced device IDs 2018-12-27 00:59:44 +01:00
Matthias Koefferlein 195324295d WIP: tests for new net predicates. 2018-12-25 20:56:08 +01:00
Matthias Koefferlein 4f8416766c WIP: renamed port -> terminal for devices. This is correct technical term. A port is a two-terminal entity. 2018-12-25 20:19:37 +01:00
Matthias Koefferlein e3b795e334 Unique ID of device class objects, netlist reference in device class. 2018-12-24 13:52:17 +01:00
Matthias Koefferlein eb6b043c3b Parameter values of db::Device/db::DeviceClass 2018-12-24 13:39:19 +01:00
Matthias Koefferlein c5222c26e3 Added DevicePortProperty class with tests and GSI binding 2018-12-24 01:31:06 +01:00
Matthias Koefferlein aa5e885215 Added Ruby tests for GSI binding of db::Netlist classes 2018-12-24 00:08:34 +01:00
Matthias Koefferlein 3c2c72d9ed WIP: GSI binding of db::Netlist at al 2018-12-23 22:31:26 +01:00