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iverilog/tgt-vhdl
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Nick Gasson 0e458501b3 Ensure binary operands have correct signedness 
Previously only signedness was only corrected for the
result. This patch ensures the VHDL operands have the
same signedness as their Verilog counterparts.

This fixes a few of the signedX tests.
2008-08-28 21:53:12 +01:00
..
vhpi
…
cast.cc
Finish cast.cc cleanup
2008-08-27 16:59:05 +01:00
configure.in
…
display.cc
Avoid printing field widths in $display/$write output
2008-08-15 19:43:16 +01:00
expr.cc
Ensure binary operands have correct signedness
2008-08-28 21:53:12 +01:00
logic.cc
Handle BUFIF logic when vector inputs
2008-08-18 15:48:07 +01:00
lpm.cc
Implement IVL_LPM_REPEAT
2008-08-18 15:34:58 +01:00
Makefile.in
Split logic device code into separate file
2008-07-30 10:13:08 +01:00
process.cc
Use ivl_process_* functions for file/line number information
2008-08-02 10:44:03 +01:00
scope.cc
Catch case where component name and instance differ only in case
2008-08-22 20:20:17 +01:00
stmt.cc
Add more warnings about untranslatable constructs
2008-08-22 20:25:58 +01:00
support.cc
Support conversion of (un)signed to std_logic
2008-08-22 20:59:14 +01:00
support.hh
Support conversion of (un)signed to std_logic
2008-08-22 20:59:14 +01:00
vhdl_config.h.in
…
vhdl_element.cc
Compress support function definitions a bit
2008-07-19 21:04:52 +01:00
vhdl_element.hh
Compress support function definitions a bit
2008-07-19 21:04:52 +01:00
vhdl_helper.hh
Handle '?' in vl_to_vhdl_bit
2008-08-11 13:53:42 +01:00
vhdl_syntax.cc
Use case-insensitive string comparison for get_decl
2008-08-22 20:15:45 +01:00
vhdl_syntax.hh
Refactor and clean up cast.cc
2008-08-27 16:47:07 +01:00
vhdl_target.h
Avoid generating useless `wait for 0ns' statements
2008-08-05 11:02:36 +01:00
vhdl_type.cc
Generate VHDL array type declarations of Verilog arrays
2008-07-17 13:08:55 +01:00
vhdl_type.hh
Generate VHDL array type declarations of Verilog arrays
2008-07-17 13:08:55 +01:00
vhdl.cc
Finish re-writing nexus code
2008-07-29 19:33:40 +01:00
vhdl.conf
…