fc44658dad
Handle empty argument list to system function. (SystemVerilog)
2011-11-06 09:13:09 -08:00
8e0beff3ab
Handle arrays of vectors in VHDL types.
...
This incidentally adds binding of generic to generic instantation.
2011-11-06 09:01:02 -08:00
c1be255844
Fix dump display of array ranges.
2011-11-05 17:22:30 -07:00
cc508d1626
Support write_to_stream for arithmetic expressions.
2011-11-05 15:55:41 -07:00
2063c5ee9d
Support VHDL user defined array types.
2011-11-05 15:55:17 -07:00
98d928f6e0
Add support for VHDL for-generate
2011-10-30 17:10:19 -07:00
5724f71339
Elaborate expressions for entity generics.
2011-10-29 17:07:03 -07:00
15da45f7cb
VHDL initialization expressions for signals.
2011-10-29 17:06:40 -07:00
37ef14b1c8
Implement VHDL conf_std_logic_vector() as SystemVerilog size cast.
2011-10-29 14:47:39 -07:00
4f98a6d181
Rewire VHDL addition expression parsing.
...
The VHDL LRM addition expression rules are ... different.
2011-10-23 17:31:58 -07:00
2be682f8a5
Support VHDL component instantiations with generics as Verilog parameters.
2011-10-23 17:08:48 -07:00
eeeadea3ac
Fix recently broken write of vhdl packages to work space.
2011-10-16 12:18:34 -07:00
a109df04bb
Proper expression type for vhdl relation expressions.
2011-10-16 11:02:07 -07:00
93e5a72d84
Get parameter output syntax right for vhdlpp.
2011-10-16 11:01:32 -07:00
d9acfe57b1
Put off array bound evaluation / describe entity generics as parameters
...
Entity generics are easily implemented as module parameters, so make
it so. Give the parameters their default values from the generic declaration.
Array bounds may use values that cannot be evaluated right away, so
put off their evaluation.
2011-10-15 17:41:48 -07:00
a6f63b8a54
Parse generic clause in entity headers
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The generic clause can create named generics in entities. This patch
gets the parser support for them working, even though they cannot
yet evaluate.
2011-10-15 09:49:24 -07:00
6268db6e68
Handle simple type declarations.
2011-10-09 15:25:35 -07:00
30cfcbe2dc
Rework elaborate/emit of types.
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This rework is needed to reasonably handle new types, like enums.
2011-10-02 10:56:00 -07:00
271aaf6376
Parse enumeration type declarations.
2011-10-01 17:04:04 -07:00
8003382b3e
Elaborate and emit case statements.
2011-10-01 11:45:28 -07:00
cff0deeacc
Update lxt_write and lxt2_write files from GTKWave
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Update the lxt_write.[ch] and lxt2_write.[ch] files to the latest from
GTKWave. This is just comment changes.
2011-10-01 09:48:41 -07:00
3b6e26aa90
An enumeration cannot have duplicate values.
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Add code to check that an enumeration does not have duplicate values.
2011-10-01 09:32:37 -07:00
be1be31deb
Update some cppcheck suppressions and fix one problem in the code.
...
Update the line number for a couple cppcheck suppressions and add one for
the pool variable in the vvp directory.
Also move a check for null to the correct place.
2011-09-29 09:40:40 -07:00
c59d27e19f
Remove more clang warnings.
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clang warns that the yyinput function generated by flex is never used.
2011-09-25 10:14:16 -07:00
eab5bacf9f
Remove clang/clang++ warnings.
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This patch makes the code consistently use struct/class in the C++ files,
it removes a couple shadow warnings and where a class pointer is passed to
the C routines, it defines the pointer as a class for C++ and as struct for
C and it removes a namespace std duplication.
2011-09-25 10:14:04 -07:00
609c038484
Add more support for signed enumerations in SV.
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This patch add support for passing if the enumeration is signed or not
to the run time. This is really only needed for debug and VPI access.
2011-09-25 09:56:02 -07:00
52019b0e55
Merge branch 'master' into work8
2011-09-18 19:48:50 -07:00
88cce86c63
Emit code for the to_unsigned() bulit-in function.
2011-09-18 19:31:28 -07:00
557e331ce1
Support SystemVerilog size cast.
2011-09-18 19:21:46 -07:00
873a447b5c
Evaluate VHDL <name>'length attribute at compile time.
2011-09-18 17:45:06 -07:00
677a22d353
Generate code for vhdl for loops.
2011-09-18 15:51:31 -07:00
f0e61a1db7
Basic vhdl elaboration for unary not operator.
2011-09-18 15:13:30 -07:00
f4217af506
ostream operator for perm_string objects.
2011-09-18 15:12:51 -07:00
4d445dc269
Fix parse of unnamed processes.
2011-09-18 09:37:11 -07:00
766bf45dcf
Fix long division.
...
On a 64-bit machine the following module shows incorrect division
results:
`define X {4'b 1000, `N'b 0}
`define Y {1'b 1, `N'b 0}
module b;
reg [`N:0] y = `Y;
reg [3:0] z1, z2;
initial begin
z1 = `X / `Y;
z2 = `X / y;
$display("%3d %b %b", `N, z1, z2);
end
endmodule // b
$ for N in {60..65}; do /usr/bin/iverilog -DN=$N -oa b.v && /usr/bin/vvp a; done
60 1000 1000
61 1000 1000
62 1000 0111
63 1000 0101
64 1000 1000
65 1000 1000
The first chunk of the patch (result -> tmp_result) fixes this:
$ for N in {60..65}; do iverilog -DN=$N -oa b.v && vvp a; done
60 1000 1000
61 1000 1000
62 1000 1000
63 1000 1000
64 1000 1000
65 1000 1000
The second chunk fixes
`define X 264'h 800000000000000000000000000000000000000000000000000000000000000000
`define Y 192'h c6df998d06b97b0db1f056638484d609c0895e8112153524
module c;
reg [191:0] y = `Y;
reg [72:0] z1, z2;
initial begin
z1 = `X / `Y;
z2 = `X / y;
$display("%x %x %b", z1, z2, z1 == z2);
end
endmodule // c
$ /usr/bin/iverilog -oa c.v && /usr/bin/vvp a
0a4c4a2c1dacd76220c 0809033397ca3427927 0
$ iverilog -oa c.v && vvp a
0a4c4a2c1dacd76220c 0a4c4a2c1dacd76220c 1
2011-09-17 18:35:25 -07:00
f0bf64271b
SystemVerilog has more lax rules for function declarations.
...
Allow empty parameter lists
Allow lists of statements instead of simple statements.
2011-09-17 12:10:05 -07:00
1d02f89a09
Handle vhdh array aggregate expressions.
...
Support the more general case of explicit element expressions
defined at various index positions, mixed with "others" records.
2011-09-11 17:08:22 -07:00
3497e2e663
Distinguish bit selects of entity ports from function calls.
...
Besides variables and signals, a name with a bit select may
be an entity port. Distinguish these from function calls.
2011-09-11 15:28:58 -07:00
64e16d34f3
Add vhdl_sys.vpi to the make clean target
2011-09-11 12:08:06 -07:00
8383188292
Add support to dump the two-state variables.
...
Add support to dump the two-state variables (bit, byte, short, int and
long) using the fst, lxt, lxt2 and vcd dumpers.
2011-09-11 12:07:02 -07:00
dd9962c221
The two-state variables are in the vpiVariable category.
...
Add all the two-state variables (bit, byte, short, int and long) to
the vpiVariable category.
2011-09-11 12:04:03 -07:00
507621ef30
Update $scanf, $printtimescale and the general is_numeric check for 2-state
...
This patch updates the $scanf and $printtimescale routines to work with
two-state variables. It also updates the general is_numeric check to
recognize two-state variables as numeric.
2011-09-11 11:58:16 -07:00
746a21b437
Update the $random routines to allow an int, long or bit as a seed.
...
Modify the $random code to allow the seed to be either an int, long or
bit that is 32 bits or longer. The 32 bit check is new and also applies
to reg/logic variables.
2011-09-11 11:58:09 -07:00
dc0e66ab90
Update $clog2() to add support for two-state variables.
...
The $clog2() routine can consider any two state variable argument
as numeric.
2011-09-11 11:57:50 -07:00
57f296455a
The $value$plusargs() routine can put to a two-state variable.
...
Update the $value_plusargs() routine so it can put the extracted value
to a two-state variable.
2011-09-11 11:57:30 -07:00
e7a705d8e6
The $queue routines can use two-state variables.
...
Update the various $queue routines to use the appropriate two-state
variables depending on the context.
2011-09-11 11:57:08 -07:00
45d8925ad2
Add the ability to $display and $monitor a bit, byte, short, int or long var.
...
Add code so that we can $display and $monitor the two-state variables.
2011-09-11 11:53:19 -07:00
9fb317a4e1
A vpiBitVar can have a non-zero LSB and can be unsigned.
...
The general bit variable can be either signed or unsigned and can
have a non-zero LSB.
2011-09-11 11:47:39 -07:00
4f8cace5a9
Add the ability to place callbacks on bit, byte, short, int and long variables.
...
You can place a callback on the new SystemVerilog 2-state variables.
2011-09-11 11:46:25 -07:00
40c37be307
Display the type name for bit variable (vpiBitVar).
...
Display vpiBitVar instead of 620 when asking for the type name of a
bit variable.
2011-09-11 11:42:46 -07:00
Stephen Williams
Cary R
Martin Whitaker
Alexander Klimov