SystemVerilog allows a variable to be used as a variable OR
as an unresolved wire. The detection of this case was checking
the references to the affected value, instead of the l-value
references.
(cherry picked from commit cceeaa30f27260cd444015cb39b04353cb858768)
The final step of expression elaboration is to reduce the width of
lossless/unsized constant expressions to the minimum needed to hold
the resulting constant value. This leads to unexpected results if
the user supplies a literal number with redundant digits that gets
passed to a system task that is sensitive to the width (e.g. $display).
This patch prevents width reduction occurring in this case.
When a conditional statement is unnamed, it doesn't create a scope
and we get into "direct" generate scheme elaboration. This direct
elaboration needs to handle case generate schemes.
The IEEE standard does not specify the behaviour of a tranif primitive
when its control input is an 'x' or 'z'. vvp currently treats these as
if the tran was turned off, but it would be better to propagate the
uncertainty to the tran bi-directional ports. For compatibility with
other simulators, we adopt the behaviour specified for MOS primitives.
This is a cleanup in preparation for better support of range lists.
(cherry picked from commit 8f7cf3255acad55841f8b3725e3786ef49daad68)
Conflicts:
PTask.h
elab_scope.cc
elab_sig.cc
parse.y
pform.cc
pform.h
pform_types.h
Signed-off-by: Stephen Williams <steve@icarus.com>
The SystemVerilog unbased literals (e.g. '0, '1, etc.) are expected to be
used standalone and cannot take a size. This patch modifies the parsing
code to give a good error message when this is done.
The standard specifies that the size of a vecval should be calculated as
(size - 1)/32 + 1. When size is a PLI_INT32 this is needed to prevent an
overflow, but when the size is unsigned this can be simplified to
(size + 31)/32 since the size must fit into an integer, but we have an
extra significant bit in an unsigned so no overflow can happen.
This patch changes the code to use the correct version of the equation
depending on the context.
The previous patch does this in vvp/vpi_priv.cc
When vpi_put_value() is asked to delay the assignment any pointer data
needs to be duplicated so that the caller can clean up the locally
allocated memory without causing memory access problems.
Also update word calculation to match the next patch.
If a tranif gate has a delay, the vvp code generator needs to generate
a unique label for the island port used for the tranif enable, to
prevent a name collision if the undelayed signal is also connected
to the island.
Also add an assertion in vvp to catch bugs like this.
Class methods belong in a class scope, not the containing module.
So create a lexical scope that carries tasks and functions and
create a PClass to represent classes.
Tasks call arguments may be dropped in favor of default values.
Allow for that in the syntax. This requires a little handling
of the non-SystemVerilog case during elaboration.
Class names can be declared early, before definitions, so that the
name can be used as a type name. This thus allows class definitions
to be separate from the declaration. This creates some complexity in
the parser, since the lexor knows about the class names.
This adds the vector_type_t and real_type_t types to handle
vector and real types in tf_port items. This cleans up a lot
of the parsing for these items.
During parse/pform processing, convert increment statements to
the equivalent compressed assignment statement. This is less weird
for elaboration processing and better expresses what is going on.
Stephen Williams
Martin Whitaker
Gordon McGregor
Cary R
Larry Doolittle