When a black-box item requests a specific footprint, we need to
read a file (<footprint>.fp) that contains the actual details
about that footprint. Support parse of that file and use the
loaded Element to generate the footprint for the item.
On some systems having both %.o: %.c and %.o: %.cc rules confused the
make system. This is directory only has C++ code so remove the %o: %.c
rule. Also the C++ compiler should be used to link C++ object code.
On Ubunto 10.10 (32 bit) tgt-pcb would not build because there were
include file issues. This patch fixes those and uses the C++ include
version where appropriate.
The main .pcb file contains elements, and basic PCB status.
Write out a .pcb file with stub Elements for each of the devices
in the design.
Rearrange the way the files are reported to the code generator
so that we can sensibly express where the output files are.
This is a pretty trivial fix for the code generation of compressed
assign to a memory word. We generated incorect code for the stash
of the calculated word index, causing the assign of the result to
not work properly.
This same change was done in the vpi directory. This patch fixes the
issues in the libveriuser directory. This fixed a fail in the vpi
timescale test under MinGW.
A declaration of the form "parameter signed a = 1.0" causes a
compiler crash. The standard is somewhat contradictory on what
type "a" should have, but testing with other compilers shows a
majority in favour of it being a real value.
The standard allows a parameter (or localparam) declaration of the
form "parameter signed my_param = ...". The parser currently rejects
this. A small adjustment is also required in the parameter evaluation
code to correctly apply the type.
Now we have a code generator that can handle compressed assignments
as they have been re-imagined in elaboration. There are some cases
that are not yet supported, we'll patch them up in due course.
Most people doing real modeling don't want to bring in the whole
Verilog-AMS infrastructure to use wreal nets. This patch adds the
wreal keyword to the xtypes generation so that wreal is available
by default.
This patch adds wreal support when in Verilog-AMS mode. It doesn't add
everything that is shown in the Verilog-A standard.
It adds the following:
Declaring a wreal net.
Declaring a wreal net with an initialization.
Declaring a wreal input/output using ANSI syntax.
Declaring a wreal input/output using the old style.
Declaring wreal inout ports are also allowed and parsed, but the
compiler does not know how to handle this. There are other deviations
from what is shown in the Verilog-A standard, but this should get most
of the syntax people actually use.
An @* with no sensitivities should be treated as something that will
never trigger vs something that will run continuously. This patch makes
this change and adds a warning when an @* has no sensitivities since
this is almost certainly a coding bug.
It is legal for a named block to contain variable definitions and
no statements. This patch fixes this for both style of blocks. It
also organizes the block parsing code to be a bit more clear, adds
an error case for fork/join and changes on check for size() > 0 for
the more efficient ! empty().
To avoid a variables not initialized in the construct this patch modifies
the PSpecPath class to take the polarity and full_flag as arguments to
the constructor.
The --always flag to git describe is harmless in the normal case,
and helpful in some special cases. Also add the --dirty flag to
get extra interesting details.
If a wired and/or net has more than four connections all the other
resolution branches must also be wired and/or. All other nets can
just be tri since tri0/tri1 only needs the final resolution to be
an active pull up/down.
Since synthesis is not currently supported we do not support/generate
sync/async set or clear control inputs. This is further complicated by
the fact that the VVP DFF primitive is not fully implemented.
This patch fixes a compile problem in Cygwin where there are two
definitions for abs() that do not match so the C++ code doesn't know
which one to call. To avoid the whole mess replace the call to abs()
with the appropriate ?: construct.
In a specify block a full connection is defined to only support a single
source and destination path. This patch adds an error message when this
is found, except we skip the error if all the paths are a single bit
wide. This exemption was added to match the functionality found in
NC-Verilog and presumably Verilog-XL.
A message was also added in place of an assert if the source signals was
not found in the current scope.
Both UDPs and system functions use the wide input functor. This patch
modified the code generator to create a local net declaration for the
output net if we have either a delay or modpath connecting the output
to the true output. This is needed so that the wide input can be
cleaned up correctly.
Local real nets were also added to the local net pool when testing with
valgrind. This allows them to be cleaned up at the end.
For a delay we do not know exactly what type we will be propagating
until the initialization event has happened. Because of this we
allocate both a vec4 and a vec8 value. Once the initialization event
has happened we can free the unneeded element(s).
Cary R
Stephen Williams
Martin Whitaker