8ea3b6b0b8
header includes for gcc-4.3 compatibility
...
minimal changes required to build without error
tested with gcc-4.3 (Debian 4.3-20071130-1) 4.3.0 20071130 (experimental)
2008-01-04 16:14:44 -08:00
64936d07e5
Add %ix/getv instruction
...
The %ix/getv instruction loads an integer register directly from
a signal vector. This is an optimization that an index register
is loaded from an expression is only a signal. It avoids the thread
vector space.
2007-12-07 13:12:19 -08:00
3b90a827e5
Fix simple compile warnings.
2007-12-04 22:14:26 -08:00
8f519531f3
Optimize load-add with load/add instruction
...
Where and expression is an immediate value added to a signal value,
it is possible to optimize them to a single instruction that combines
the load with an add at the same time.
2007-12-04 19:15:15 -08:00
68a9526fec
Minor performance tweak of vector_to_array function.
2007-12-02 19:00:12 -08:00
9759c19734
Implement release of linked force nodes
...
When nets are forced by non-constant expressions, the value is linked
to the destination net through a force_link. This patch adds the code
needed to unlink a force/link so that release and new force/links can
work. This fixes pr1735836.
Signed-off-by: Stephen Williams <steve@icarus.com>
2007-11-13 19:35:44 -08:00
acdbe274f9
Fix signed ocmpare of negative numbers.
...
signed compare in proceedural code was comparing the absolute
value if both operands were negative. Wrong!
Signed-off-by: Stephen Williams <steve@icarus.com>
2007-10-03 22:26:42 -07:00
5d750b7779
Optomize runtime using immediate compare
...
Implement compare-immediate instructions and generate code to use
these new instructions to improve runtime performance.
Signed-off-by: Stephen Williams <steve@icarus.com>
2007-10-03 20:58:40 -07:00
e75e7131ac
Fix signed compare with minus values
...
If the operands were negative, and not equal, the lt flag
would be set incorrectly.
Signed-off-by: Stephen Williams <steve@icarus.com>
2007-07-02 21:33:05 -07:00
d7c3a32b06
Fix code generation for real expressions
...
Real value are vector width of 1, fix real literal to reflect this.
fix leaking real registers in code generation for function arguments.
Load of signal should handle conversion from real to vector. Function
arguments, type vector passed a real value, are an example where this
comes up.
Signed-off-by: Stephen Williams <steve@icarus.com>
2007-06-29 21:10:37 -07:00
e24e77660f
Detect and use the nan function.
2007-06-13 01:03:57 +00:00
ae82eccdc4
handle constant inf values.
2007-06-12 02:36:58 +00:00
0a38499941
Properly handle signed conversion to real
2007-06-07 03:20:15 +00:00
55f8e5d364
int vs long expressions on 64bit arch (ldoolitt)
2007-06-05 21:52:22 +00:00
9931e4c013
Finish up part select of array words.
2007-04-14 04:43:01 +00:00
4f74d9df98
Add the mov/wr opcode.
2007-02-14 05:58:14 +00:00
d958a4a5af
Handle relink of continuous assignment.
2007-02-05 01:08:10 +00:00
85ceea7358
Fix missing check for thread bits width in ADDI
2007-01-31 22:28:55 +00:00
91d84e7dc7
Major rework of array handling. Memories are replaced with the
...
more general concept of arrays. The NetMemory and NetEMemory
classes are removed from the ivl core program, and the IVL_LPM_RAM
lpm type is removed from the ivl_target API.
2007-01-16 05:44:14 +00:00
26e2e85ffa
Handle non-constant delays on indexed non-blocking assignments.
2006-10-05 01:23:53 +00:00
50800fd3a1
Add support for real valued modulus.
2006-08-09 05:19:08 +00:00
fc0695beb6
Handle 64bit delay constants.
2006-08-08 05:11:37 +00:00
898b0e0365
Support release of a for/linked reg.
2006-08-04 04:37:37 +00:00
36039e13ec
schedule takes relative, not absolute, time.
2006-04-27 04:38:00 +00:00
d0de678d57
real-to-integer conversions round, not truncate.
2006-02-02 05:48:45 +00:00
d434dd7296
Allow part selects of memory words in l-values.
2006-02-02 02:43:57 +00:00
2b8fd28a95
Force instruction that can be indexed.
2005-11-26 17:16:05 +00:00
35951510c5
Put vec8 and vec4 nets into seperate net classes.
2005-11-25 17:55:26 +00:00
be73be8c98
Spelling patches from Larry.
2005-09-19 21:45:35 +00:00
988a0a7048
Add the load/v.p instruction.
2005-09-17 04:01:01 +00:00
65584e6dde
Add word integer compares.
2005-09-14 02:50:07 +00:00
efd7825964
minor correction to address check in of_MOV1XZ
2005-08-30 00:49:21 +00:00
7c19eb51e7
Minor cleanup.
2005-08-29 04:46:13 +00:00
5cf2ce6499
Fix bit destination address in of_AND
2005-08-27 03:28:57 +00:00
bc489a7761
Bring threads into the vvp_vector4_t structure.
2005-08-27 02:34:42 +00:00
de1dd2f2b3
Make bit masks of vector4_t 64bit aware.
2005-06-26 01:57:22 +00:00
1b30bac9f3
Optimize the LOAD_VEC implementation.
2005-06-19 18:42:00 +00:00
cd14ee77ae
Add the assign_v0_d instruction.
2005-06-14 01:44:09 +00:00
fb8ddbbfde
Remove useless references to functor.h
2005-06-12 01:25:27 +00:00
42433f4df9
Add support for notif0/1 gates.
...
Make delay nodes support inertial delay.
Add the %force/link instruction.
2005-06-02 16:02:11 +00:00
d6a89a40cf
Clean up instruction type reverences to bits.
2005-05-17 20:51:06 +00:00
5277124c76
Implement non-blocking part assign.
2005-05-07 03:15:42 +00:00
2894cdefc7
Add cassign/link instruction.
2005-05-01 22:05:21 +00:00
d8a456bd67
The indexed set can write a vector, not just a bit.
2005-03-22 05:18:34 +00:00
8e135a1020
Non blocking assign to memory words.
2005-03-06 17:07:48 +00:00
e7c2e06260
Check that lead.mv vector width matches word.
2005-03-05 05:45:18 +00:00
85286cc086
Rearrange how memories are supported as vvp_vector4 arrays.
2005-03-03 04:33:10 +00:00
c5e7e2ec0a
Signals may receive part vectors from %set/x0
...
instructions. Re-implement the %set/x0 to do
just that. Remove the useless %set/x0/x instruction.
2005-02-14 01:50:23 +00:00
355ead0002
Add debug dumps for vectors, and fix vvp_scaler_t make from BIT4_X values.
2005-02-12 06:13:22 +00:00
a121e703f3
Add vector4 implementation of .arith/mult.
2005-01-28 05:34:25 +00:00
Larry Doolittle
Stephen Williams
steve