15cda5fef2
Fix subtle issues related to fork/join of tasks.
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When a fork/join contains a task, the task completion may become
confused with the completion of another thread if any of the
threads are embedded in the main thread. So always create threads
for all the fork paths, and joins to match.
2013-08-29 20:31:26 -07:00
a10e07908e
Precompile vhdlpp/lexor_keyword.gperf in autoconf.sh
2013-08-28 14:53:29 -07:00
c2c9e09a49
snapshot 20130827
2013-08-27 19:55:20 -07:00
1b79df810f
Handle DFF with clock-enable in blif code generator
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In the ASIC universe, it is (probably) OK to replace a DFF CE
with a mux of the D input with the Q output. The idea is that
if the CE is true, the DFF latches D, but if CE is false, the DFF
re-latches the current output.
2013-08-25 12:27:57 -07:00
9dde4b705d
Detect and synthesize FF clock enables.
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Too bad BLIF doesn't support 'em.
2013-08-25 12:27:57 -07:00
1abf4f1aa1
Rework synchronous statement synthesis.
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This changes the flow of the NetProc::synth_sync method, and
implements the NetBlock::synth_sync better.
2013-08-25 12:27:57 -07:00
a47447610f
Replace svector with vector in synth_sync methods.
2013-08-25 12:27:56 -07:00
d209d8ee39
blif support for IVL_LPM_FF devices.
2013-08-25 12:27:56 -07:00
8117f4b383
NetCase synth async measure width from map, not output.
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Make sure the NetMux device has an output that is a net.
2013-08-25 12:27:56 -07:00
6b5ae5e4db
Force calculation of blif_nex_data_t width for lib_mux_s1 devices.
2013-08-25 12:27:56 -07:00
a40c8f6bca
Cleanup/simplify mux synthesis
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Do not create useless NetNet objects for the inputs to the mux.
The synthesizer should already be creating these objects.
2013-08-25 12:27:56 -07:00
a6fb6be8b5
blif code generator support for arbitrary MUX devices.
2013-08-25 12:27:56 -07:00
ec99faff05
synthesis support for case statements with default cases.
2013-08-25 12:27:56 -07:00
1352abfc98
Fix up NetCondit synthesis to handle complex if/else clauses.
2013-08-25 12:27:56 -07:00
687d0a928b
Initial support for NetCondit synth_async.
2013-08-25 12:27:56 -07:00
947d642da7
Always turn on ivl synthesis for blif target.
2013-08-25 12:27:55 -07:00
1cbd6c3a80
Expand the scope of the parent variable.
2013-08-23 15:28:54 -07:00
11be93ce55
Merge branch 'master' of github.com:steveicarus/iverilog
2013-08-12 19:50:52 -07:00
aaf35ca6ab
Fix blif handling of wide ligic gates.
2013-08-12 19:50:32 -07:00
4294a47cec
Merge branch 'master' of github.com:steveicarus/iverilog
2013-08-12 16:37:05 -07:00
b983d5546b
Fix cppcheck call in tgt-blif (use .cc instead of .c)
2013-08-12 16:35:45 -07:00
ed9a3c3b10
Merge branch 'master' of github.com:steveicarus/iverilog
2013-08-09 20:55:44 -07:00
d8f4ff4b57
Remove eval_expr during PEBinary elaboration
...
Turns out that call to eval_expr is redundant, and in degenerate
situations can lead to so many wasteful calls to eval_expr that
elaboration performance suffers dramatically.
2013-08-09 20:55:18 -07:00
af29735f44
Update cppcheck suppression file to match latest fstapi.c
2013-08-09 11:34:29 -07:00
638300045c
Update to latest FST API files from GTKWave
2013-08-09 11:34:16 -07:00
71552b7d1a
Fix typo in verilog.spec it should be blif.tgt not blif.txt
2013-08-06 17:17:10 -07:00
7c0a75cf0c
tgt-blif is C++ so use the extra C++ warning flags
2013-08-06 17:10:52 -07:00
f054500fe2
Fix space issues in tgt-blif
2013-08-06 17:09:37 -07:00
6684b2db04
Add BLIF support for ternary (MUX) operators.
2013-08-01 17:28:04 -07:00
999a53ab75
Add blif LIB_RE_* gates support.
2013-08-01 17:28:04 -07:00
534d44ba55
blif support for bit selects.
2013-08-01 17:28:04 -07:00
c7c10613d7
blif support for unsigned magnitude comparison.
2013-08-01 17:28:04 -07:00
dfc44db0ef
BLIF support for IVL_LPM_CMP_EQ and IVL_LPM_CMP_NE
2013-08-01 17:28:04 -07:00
7a6192b5c8
Generate blif code for IVL_LPM_SUB device.
2013-08-01 17:28:04 -07:00
05f90bcf55
Support blif emit of IVL_LPM_ADD device.
2013-08-01 17:28:04 -07:00
1be59d8ae7
Add blif target to RPM package.
2013-08-01 17:28:04 -07:00
b4dbb81af7
Fix handling of certain constants in ivl_target.h API.
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The construction of the ivl_design_t consts member was broken,
not properly handling the addition of new objects.
2013-08-01 17:28:04 -07:00
e709849243
Add a README-BLIF.txt file for the blif target.
2013-08-01 17:28:04 -07:00
1b2fa39cdc
Add some more basic logic gates to blif target.
2013-08-01 17:28:04 -07:00
b4ec36ec78
blif nex_data_t collects name data early.
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It is possible for the get_name_index() method to be called before
the get_name() method, so need to handle that case.
2013-08-01 17:28:04 -07:00
dddaacc6fd
Follow non-canonical bit numbering.
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The signal bit numbering should be used for signals. This is
necessary for .model ports because the user specified numbers
are part of the interface, but once that is done, it is trivial
to follow it internally as well.
2013-08-01 17:28:03 -07:00
e0c9efd129
Implement blif support for constants and some logic/lpm gates.
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This starts the handling of various logic gates.
2013-08-01 17:28:03 -07:00
01b81e0dbc
Implement the ivl_target ivl_scope_child functions.
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These are a more convenient way of iterating through child scopes.
2013-08-01 17:28:03 -07:00
d2034a6458
Initial BLIF code generator.
...
Add the -tblif code generator target, and include some basic
useful behavior.
2013-08-01 17:28:03 -07:00
c4edbda969
Warn that the SystemVerilog array querying functions are not supported.
2013-07-31 19:40:25 -07:00
f3917778bc
vlog95: Add some support for $signed()/$unsigned() in a CA
2013-07-29 10:26:56 -07:00
032f12af45
Fix some sign information in the CA code.
2013-07-29 10:26:49 -07:00
bb37b74f98
Fix for br884 (packed array access problems)
2013-07-28 13:24:57 -07:00
817a38494c
vlog95: add support for zero argument functions and better named block detect
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Add support for translating a zero argument function by adding a dummy
argument and improve the code that looks for a named block in a process.
2013-07-24 19:41:59 -07:00
d6fe6ea936
Add support for calling a user functions as a task (SV)
2013-07-24 19:38:00 -07:00
Stephen Williams
Cary R