The package emit of types and constants needs to know which names are
from the current type and which are imported from libraries. Rework
the scope handling of those names so that the information is preserved.
In generate for blocks, there is a genvar that can be used in
expressions within the generate block. Generate this genvar in
the generated output, matched to the generate scope.
Elaborate records and emit them as packed SV records. Also handle
record members so handle name prefixes.
While we are at it, handle some cases of array aggregate expressions.
Port map aspects were held in std::maps. Because
of that, in case of multiple assignments to the same
port, some assignments were lost and in effect vhdlpp
produced correct verilog code from a buggy VHDL.
Std::map was replaced by std::multimap. Thanks to it
we can gather this multiple assignments and detect them
in the elaboration phase.
This function is for the time being used in the
component instatiation. It is checked, whether
an expression is a correct r-value.
To be a correct r-value, it must be either
port name or signal name.
When a signal (or port) is assigned by a sequential assignment,
the signal or port becomes a reg, instead of a wire(net). Detect
this distinction during elaboration and generate the correct
signal/port declaration.
R-value expressions are more general then L-value expressions, in that
the expression type may be a bit more complex. If the R-value expression
is part of an assignment, then elaborate with the constrained type from
the L-value. In other cases, where the expression type is not as obvious,
use expression type probes to figure out the type of the expression and
elaborate using that calculated type.
VHDL doesn't have a direct way to express "always @(posedge...)"
statements, but we do want to detect common paradigms that naturally
translate. This makes for a better translation.
Entity output ports may be used as l-values in a process within
the bound architecture. Detect that case during elaboration and
adjust the signal declaration so that it works in the Verilog pass.
Make sure in a conponent instantiation that the instantiated
component is really declared, and that the ports of the binding
really do match the ports of the declared component. This requires
that we create and save component declarations, and that components
have methods for mapping the ports.
These signals are declared in the architecture and are local to
the module. The Architecture already parsed and stored these signal
declarations, but this patch adds the ability to actually emit these
signals in the generated code.
In the process of doing this, I had to regularize the elaboration
and emit of VTypes, so that it can be used in multiple places, not
just in entity headers (for ports).
I also added support for bit selects of signals. This effected a couple
places in the parser, and expressions in general.
Martin Whitaker
Cary R
Larry Doolittle
Maciej Suminski
Stephen Williams
Arun Persaud
Pawel Szostek