The power (**) and shift operators are different from other binary
operators because their expression width calculations rely only on
their left operand, with their right operand self-determined. Get
the handling of these operators out of the PEBinary base class to
prevent confusion.
Verilog generate schemes support a special case where conditional
generate schemes that contain only a nested conditional generate
scheme do not create a new scope. Instead, it relies on the nested
generate scheme to generate the scope.
The goal is to completely remove the svector class because the standard
vector class works perfectly well. This removes the uses in the Module.h
header file.
Signals may have VMA disciplines attached. Make the attached discipline
visible through the ivl_target.h API. Also, re-arrange the internal
handling of the discipline structure so that we can expose disciplines
through the ivl_target C API without creating new structures. The
t-dll-api implementations of the discipline access functions can look
at the elaborated discipline structure directly. This is possible since
the discipline parse and elaboration are very simple.
Support arrays of realtime variable arrays and net arrays. This
involved a simple fix to the ivl core parser, proper support in
the code generator, and rework the runtime support in vvp.
The arguments of logical and/or are self determined, and the width is
fixed as 1 bit. Account for this special behavior by creating the
PEBLogic class.
Get at least basic elaboration of analog processes and contribution
statements. Bring the statements and analog statements together and
net future elaboration work sort out which statements are valid in
a given context. This makes sense because there really is a lot of
syntactic overlap, and analog behavioral code is processed somewhat
sequentially.
Put together the infrastructure for elaborating analog statements,
including create the NetAnalogTop objects that hold analog statements
and are in turn held by the design.
While doing this, clean up the various unique initial/always enumerations
to use the ivl_process_type_t type.
This patch removes all the checks for constant expressions performed
during the parsing phase, as these checks are (mostly) repeated during
elaboration. It adds the missing check in the elaboration phase (the
RHS of a register initialisation), and improves the error reporting
and error recovery in other checks.
This patch fixes pr2132552, which was caused by a fault in the parser
constant expression checking.
Currently, parameters and localparams declared in tasks, functions,
generate blocks, and named blocks are placed in the parent module
scope. Event declarations in these scopes are not permitted (a
syntax error is reported). This patch corrects this behaviour, so
that all the above declarations are accepted and are placed in the
scope in which they are declared.
Note that the IEEE standard does not permit parameter declarations
in generate blocks. This patch causes the parser to reject such
declarations.
Nothing to do with tab width! Eliminates useless
trailing spaces and tabs, and nearly all <space><tab>
pairings. No change to derived files (e.g., .vvp),
non-master files (e.g., lxt2_write.c) or the new tgt-vhdl
directory.
Low priority, simple entropy reduction. Please apply
unless it deletes some steganographic content you want
to keep.
Statements can have attributes attached to them. Handle a few cases in
the parser where attributes may be attached to statements, and get them
as far as the pform.
This patch adds blocking repeat event controls and also makes the
base repeat statement sign aware. If the argument to repeat is
negative (it must be a signed variable) then this is treated just
like an argument of 0 (there is no looping). Doing this allows us
to model the repeat event control as follows.
lhs = repeat(count) @(event) rhs;
is translated to:
begin
temp = rhs;
repeat (count) @(event);
lhs = temp;
end
This patch also pushes the non-blocking event control
information to the elaboration phase where it will report they
are not currently supported.
This patch pushes the automatic property for both tasks and
functions to the code generators. The vvp back end does not
currently support this so it will error out during code
generation. The VHDL back end should be able to use this
property and tgt-stub prints the property. Having this will
also make it easier when we do adding this to the runtime.
This patch adds the time and realtime properties for user
task and function arguments. It also make a common rule
for real and realtime since they are the same.
This patch fixes a bug where a local parameter with only a range
was incorrectly setting the default parameter type to IVL_VT_NO_TYPE.
This would create a compile time assert for any untyped
parameter/localparam immediately following it.
Contribution statements have an l-value and r-value. Parse those
expressions into pform so that elaboration has something to work with.
In this process, this patch also changes the PECallFunction class to
use the vector template instead of the svector template. The latter
doesn't add anything over the STL vector template, so this is a start
of working the svector out.
Verilog-2001 only allows a single generate item within a generate-
endgenerate region, but allowed one to collect generate schemes with
begin/end blocks. Verilog-2005 cleaned up that mess, and it is the
2005 syntax that Icarus Verilog implements. This patch detects the
anachronistic use of begin/end within the generate region, ignores
the begin/end words, and prints a warning that the user is using an
obsolete syntax.
This patch adds the time and realtime types to parameters
and local parameters. It also makes the width (range) of
an integer parameter match the variable "integer_width"
(normally 32 bits). It also converts a real value to
an integer when a range is implicitly or explicitly
given. This all matches what the standard specifies.
Fixed an error in converting -1 to a unsized verinum.
Parameter value ranges support the exclude of a point as well as
range, so add the syntax to support that case. Internally it is
handled as a degenerate range, but the parse and initial elaboration
need to know about it.
Before this, the types of parameters were always logic, only the
width and signed-ness could be controlled. A parameter may take
on implicit real values if the expression were real.
With this patch, the type for the parameter can be explicitly set
to logic or real. This also means that the parameter real valued
expressions need to be more crefully treated, possibly with casting
integral expressions to real values, or real expressions to integral
values.
Handle parameter value ranges as far as the pform. The +-inf expressions
are not handled yet, nor is the single value exclude, but the other
cases are handled.
The VAMS-2.2 LRM syntax does not include a semicolon after the nature/
discipline name, but the 2.3 LRM does. Effectively, that means that
the simicolon is option from now on.
Pform parse enough of the natures that they can be mapped and the
disciplines can bind to them. Since Verilog-AMS expects natures to
be declared before use, we can do the binding early.
The VAMS-2.3 specification says that discipline and nature declarations
have a semi-colon after the identifier, but the disciplines.vams in
the appendix does not. Initial guess what that the disciplines.vams
is correct, but I've been told that the syntax is correct and the
disciplines.vams file is not.
Parse discipline declarations, net discipline declarations, and
analog contribution statements. Don't yet do anything useful with
these, just give a sorry message where they are encountered.
This is part of the standard disciplines header file, with enough
syntax to part the natures and disciplines included. Don't do anything
with the parse results yet.
This patch adds file and line information for parameters and
local parameters. It also adds file/line stubs for signals in
the tgt-* files. It adds the pform code needed to eventually
do genvar checks and passing of genvar file/line information.
It verifies that a genvar does not have the same name as a
parameter/local parameter.
Implement in behavioral the abs/min/max operators for real values.
The parser treats these builtin functions as operators, unary or
binary, and elaborates them appropriately.
Also add enough code generator support to handle real valued expressions
in thread context.
Verilog-2005 defines the base-10 log function to be $log10. This makes
sense because in C the log() function is the natural log. So add the
$log10 function.
Since there may be legacy code that uses the $log function, leave it
defined, but we should consider at least printing a warning when the
$log function is used.
Verilog-AMS recommends that users use the system-function style
math functions, but supports traditional style math functions for
portability. Add the keywords and parse the traditional Verilog-A
functions, and handle them as calls to the equivilent system
function.
This patch does a better job of recovering from an error in a
task or function definition. This prevents the compiler from
printing many irrelevant error messages.
This patch adds the functionality to tasks/functions to handle the
declaration of multiple ports using a single ANSI declaration. It
also deletes the old range vector before it adds the new one. The
tasks and functions are different than modules so we need to copy
the range for them.
Update the rules for parsing user function definitions to allow
Verilog-2001 ANSI style port declarations. In the process, also
unify with the user task port declaration so that the types don't
diverge. The rules are the same for both, with the extra constraint
that function ports must all be input. This latter rule is checked
later, during elaboration, so that the task/function pform code
can be shared, and better error messages can be generated.
This patch fixes some allocation problems (mostly in the parser
and lexor relating to identifiers). It also fixes a couple places
where uninitialized variables were used. All found with valgrind.
There are still 100 tests that have problems. Many of these appear
to be related.
Case-generate alternatives create sub-scopes that need to be scanned
by the scope scanner in order to get function definitions etc. that
are defined lexically within generated scopes.
Move the storage of wires (signals) out of the Module class into
the PScope base class, and instead of putting the PWires all into
the Module object, distribute them into the various lexical scopes
(derived from PScope) so that the wire names do not need to carry
scope information.
This required some rewiring of elaboration of signals, and rewriting
of lexical scope handling.
All the pform objects that represent lexical scope now are derived
from the PScope class, and are kept in a lexical_scope table so that
the scope can be managed.
Modules, functions and tasks are named scopes so derive them all
from the PScope base class. These items all take scoped items, so
the eventual plan is to move these items into PScope.
Generate case is a complex generate scheme where the items are
sub-schemes of the case generate itself. The parser handles them
something like nested generate statements, but storing the case
guards as the test expression. Then the elaborator notes the
case scheme and reaches into the case item schemes inside to make
up tests, select the generate item, and elaborate.
Rework the handling of file names to use a perm_string heap to hold
the file names, instead of the custom file name heap in the lexor.
Also rename the get_line to get_fileline to reflect its real duties.
This latter chage touched a lot of files.
Using the parser supplied error token to get file and line number
information appears to give incorrect results at best and core dump
at worst. This patch uses the closest real token that makes sense
to alleviate this problem.
The min/typ/max default warning was not being produced in all
locations a min/typ/max expression could be used. This patch
adds the default warning code to all locations. It also
modifies the manual page to explicitly state that only the
first ten warnings are printed.
Most types in Icarus support a single array dimension (reals do
not support arrays at all). If you try to use an invalid number
of dimensions the parser will now display an error message.
Print out a warning if extra digits are given for sized binary, octal
or hex constants. Decimal constants are very hard since we never
calculate the true number of bits the digits represent, so for now
decimal constants are not checked.
This patch adds min_typ_max to expressions. Remember when using a
min_typ_max triplet in an expression they must be enclosed with
parenthesis (1364-2001 section 4.3 page 58).
Previously list of port declarations were considered a complete
definition of the port. This caused problems for some, so this patch
allows implicitly defined ports (no wire/reg/etc.) to have net
declarations in the body.
This patch is rather large and fixes a couple of problems. The major
change is that instead of keeping all the range specifications in
a list that is later processed the information is now kept as
individual entries for the port and net definitions. This allows
easier checking for multiple definitions (pr1660028), more
detailed error messages and the ability to pass the now deprecated
style of a scalar I/O definition used with a vectored net definition.
These changes did require extra code to prevent a single definition
from setting the range values in more than on place.
When using the new ANSI-C style of port declarations (1364-2001 12.3.4
list_of_port_declarations) the compiler ensures that you do not
redeclare the port in the body (it is already completely defined).
This caught a few errors in the test suite (pr859 and sqrt32*).
The flag to disable the normal port checking and allow the deprecated
port syntax is -gno-io-range-error. This will print a warning for the
case of a scalar port with a vectored definition in the body. All
other cases are still considered an error.
This patch adds better checking for a missing endmodule or an attempt
to nest modules. A more descriptive message is printed and the location
of the original module definition is printed.
Support initialization assignments of real value variables. In the
process, clean up the processing of real variable declarations in
the parser.
Signed-off-by: Stephen Williams <steve@icarus.com>
more general concept of arrays. The NetMemory and NetEMemory
classes are removed from the ivl core program, and the IVL_LPM_RAM
lpm type is removed from the ivl_target API.
Stephen Williams
Cary R
Martin Whitaker
Larry Doolittle
thiede
steve