Commit Graph

64 Commits

Author SHA1 Message Date
Maciej Suminski 7aab315ce5 vhdlpp: Allow assigning values to inout ports. 2015-05-20 17:30:07 +02:00
Maciej Suminski 7db01d8ded vhdlpp: ScopeBase::is_enum_name() returns VTypeEnum* instead of bool. 2015-05-07 16:28:30 +02:00
Larry Doolittle 4304fd503e vhdlpp: and_reduce() and or_reduce() functions. 2015-05-06 10:03:02 +02:00
Maciej Suminski ab9a8ccbf3 vhdlpp: Added fit_type() & probe_type() for ExpFunc. 2015-03-27 18:57:40 +01:00
Maciej Suminski e6525ec35f vhdlpp: Added a constructor for VTypeArray that takes integers as ranges. 2015-03-27 18:57:40 +01:00
Maciej Suminski 3b14797075 vhdlpp: Prefix probe for VTypeArray. 2015-03-27 14:53:43 +01:00
Maciej Suminski 807ad8002d vhdlpp: Check generics when searching through constants. 2015-03-06 20:39:10 +01:00
Maciej Suminski 1852c5ab9d Revert "vhdlpp: Support for accessing words in constant arrays."
This reverts commit 9ca754b6db.
2015-03-06 17:32:25 +01:00
Maciej Suminski 9ca754b6db vhdlpp: Support for accessing words in constant arrays. 2015-02-19 17:07:41 +01:00
Maciej Suminski e569e07d4e vhdlpp: Type 'NATURAL' is translated to 'int unsigned'. 2015-02-19 17:07:41 +01:00
Maciej Suminski 763c6fe3c9 vhdlpp: Support for shift operators (SRL, SRR, SRA, SLA).
To be done: ROR & ROL.
2015-02-17 10:15:57 +01:00
Maciej Suminski 12b4914b63 vhdlpp: ExpName resolves enum values. 2015-02-17 10:15:57 +01:00
Maciej Suminski 19ff6a434b vhdlpp: Alternative way of dealing with unbounded vectors in fuctions (instances). 2015-02-05 12:00:25 +01:00
Maciej Suminski 1a367c84b6 vhdlpp: Subprograms can have instances that take a different set of parameter types. 2015-02-05 11:25:03 +01:00
Maciej Suminski 60077f4f06 vhdlpp: ExpBitstring elaborate_expr(). 2015-02-05 11:25:03 +01:00
Maciej Suminski 25c3798248 vhdlpp: Elaborate and emit functions work with ScopeBase instead of Architecture. 2015-02-04 16:57:43 +01:00
Maciej Suminski 9ba7694484 vhdlpp: Minor assert. 2015-02-04 16:57:43 +01:00
Maciej Suminski 962330f20a vhdlpp: Functions support unbounded vectors as return type and parameters. 2015-02-04 16:57:43 +01:00
Maciej Suminski 95faed8e9d vhdlpp: Added basic support for concatenated expressions. 2014-10-15 10:51:21 +02:00
Maciej Suminski 76aab15798 vhdlpp: Minor code cleaning. 2014-10-15 10:51:21 +02:00
Maciej Suminski 1333bc54a2 vhdlpp: Support for 'left & 'right attributes. 2014-10-08 10:05:04 +02:00
Maciej Suminski fde6525acb vhdlpp: Libraries are searched for subprograms during the ExpFunc elaboration. 2014-10-01 14:56:32 +02:00
Maciej Suminski 194a950f8d vhdlpp: Elaboration of ExpFunc parameters fallbacks to the types given in the Subprogram header. 2014-09-30 15:59:46 +02:00
Maciej Suminski f5dd2ac87e vhdlpp: Aggregate expressions for records can be specified in any order. 2014-09-17 16:32:56 +02:00
Maciej Suminski 54696e0127 vhdlpp: Elaboration & emit support for aggregate initializer expressions in records. 2014-09-17 11:24:16 +02:00
Maciej Suminski 69b145e216 Minor cleaning for valgrind output. 2014-08-06 15:01:28 +02:00
Maciej Suminski 5ed60a151f Added support for real type in vhdlpp. 2014-08-06 15:00:35 +02:00
Cary R 21b24c7725 Fix more compile warnings and a minor bug 2013-07-11 19:10:25 -07:00
Stephen Williams 8487cb5616 Do a better job of figuring the vtype of an expression. 2013-06-12 14:21:36 -07:00
Stephen Williams d630e4dfe9 Elaborate VHDL entity port types/expressions.
We need to elaborate expressions so that function calls in
expressions (i.e. ranges) get bound to their proper scope.
This binding is in turn used to emit package scopes. This
is particularly interesting for ports of entities.
2013-06-12 14:21:35 -07:00
Stephen Williams 11682fc7eb Harmless cleanup of comments / initialization warnings. 2013-04-18 18:18:40 -07:00
Stephen Williams c14134aa2e Handle genvar variables in expressions.
In generate for blocks, there is a genvar that can be used in
expressions within the generate block. Generate this genvar in
the generated output, matched to the generate scope.
2012-09-07 15:14:48 -07:00
Stephen Williams 85e000ed0c Handle prefix expressions that include array index expressions. 2012-09-03 16:00:10 -07:00
Arun Persaud f5aafc32f9 updated FSF-address 2012-08-29 10:12:10 -07:00
Stephen Williams 369a0b9eca VHDL named types work in more places. 2012-05-22 17:31:27 -07:00
Stephen Williams 63b7fe059d Reword concat to handle aggregate arguments.
When concatenation expressions have aggregate arguments, we need to
get the type of the result down to the aggregate expressions so that
it can know how to interpret the elements.
2012-05-22 17:31:26 -07:00
Stephen Williams 71d2401221 Handle VHDL records.
Elaborate records and emit them as packed SV records. Also handle
record members so handle name prefixes.

While we are at it, handle some cases of array aggregate expressions.
2012-05-22 17:31:26 -07:00
Stephen Williams ae06863db1 Elaborate prefix names which may be structure variables. 2012-05-22 17:31:26 -07:00
Stephen Williams 021d944a30 Probe type of ExpName with a record prefix. 2012-05-22 17:31:25 -07:00
Stephen Williams 7eb89c5548 Parse name prefix syntax for record member reference.
When signals/variables are records, they are often referenced by
their members, using a prefix.name syntax. Parse that syntax and
generate "sorry" messages in elaboration.
2012-05-22 17:31:25 -07:00
Stephen Williams 9b816f6478 Add support for nested when/else expressions. 2012-05-22 17:31:25 -07:00
Stephen Williams 0775e36a67 Properly elaborate argument types for binary relation expressions.
The argument types of binary relation expressions are decoupled
from the return type for the expression itself.
2012-05-22 17:31:25 -07:00
Larry Doolittle 84f14dbc81 Spelling fixes to vhdlpp tree
Mostly comments as usual, but one error message is changed.
2012-05-17 16:42:03 -07:00
Stephen Williams 8e0beff3ab Handle arrays of vectors in VHDL types.
This incidentally adds binding of generic to generic instantation.
2011-11-06 09:01:02 -08:00
Stephen Williams a109df04bb Proper expression type for vhdl relation expressions. 2011-10-16 11:02:07 -07:00
Stephen Williams d9acfe57b1 Put off array bound evaluation / describe entity generics as parameters
Entity generics are easily implemented as module parameters, so make
it so. Give the parameters their default values from the generic declaration.

Array bounds may use values that cannot be evaluated right away, so
put off their evaluation.
2011-10-15 17:41:48 -07:00
Stephen Williams 873a447b5c Evaluate VHDL <name>'length attribute at compile time. 2011-09-18 17:45:06 -07:00
Stephen Williams f0e61a1db7 Basic vhdl elaboration for unary not operator. 2011-09-18 15:13:30 -07:00
Stephen Williams 3497e2e663 Distinguish bit selects of entity ports from function calls.
Besides variables and signals, a name with a bit select may
be an entity port. Distinguish these from function calls.
2011-09-11 15:28:58 -07:00
Stephen Williams 563d73e7d9 Index/part select of VHDL l-values changes expression type
The changed expression type impacts how code is generated
for the r-value expression.
2011-09-03 17:57:37 -07:00