The calculation of the required multiplexer width was incorrect for
the corner case of a single guard value of zero.
(cherry picked from commit 27213f2af8)
(cherry-picked from master branch)
Synthesis does not currently support some commonly used styles for
representing flip-flops, e.g.
q <= 0;
if (en) q <= 1;
or
if (clr) q <= 0;
if (set) q <= 1;
For now, output a "sorry" message.
(cherry-picked from master branch)
The elaborator allows the RHS of assignment to be wider than the
LHS. When using an if statement to represent a mux, this meant the
mux inputs could be different widths, resulting in an assertion
failure during synthesis. The fix is to prune the RHS to match the
LHS for each assignment. This has the benefit of minimising the
mux width.
Added various error/warning messages for behaviour not supported
in synthesis. Also give correct behaviour when multiple case item
expressions evaluate to the same constant value.
Like this:
... if (ce0) foo <= foo_in;
... if (ce1) bar <= bar_in;
Note that this is within a block, and represents multiple FF nodes
with different clock enables.
When for example assigning to foo[<x>] within a contitional, and
doing synthesis, we need to create a NetSubstitute device to manage
the l-value bit selects.
This generates an EQZ LPM device that carries the case-z-ness to
the code generator.
Also add to the vvp code generator support for the EQZ device so
that the synthesis results can be simulated.
Account for the wildcard devices in the sizer.
It shouldn't be possible, but sometimes is, that a NetCondit is
missing input nets during async synthesis. Handle this by generating
a place-holder net and printing a warning.
Better handle the case where the output for some pins comes from
an earlier assignment. This allows for multiple ways to specify
default outputs for some cases: the default: case and pre-assignment.
When conditional ports are blending (by allowing NetPartSelects be
connected together to the outputs) make sure there isn't an accidental
overlap of drivers that invalidates the process.
When a mux (NetCondit) is only writing to a part of the output
vector (and using only a part of the inputs) then blend the mux
output with the previous statement output.
If both conditions of a NetCondit device assign to the same subset
of l-value bits, then generate a smaller NetMux device that only
switches the affected bits.
In a design, there may be lingering NexusSet objects, or the
nodangle may itself use NexusSet objects. This creates links,
and this should not confuse the functor.
While we are at it, clean up some handling of events structures.
It is possible for an assignment statement to be part of a
grander complex that has lots of outputs, not all handled
by this particular assignment. In that case, the assignment
may need to figure out which output it is supposed to bind to.
This required keeping for-loops as actual things through the
netlist form so that the synthesizer can get at and understand
the parts of the for-loop. This may improve vvp code generation
in the future, but for now continue to present to the vvp code
generation the block-while form.
Some types, i.e. vector types with parameterized dimensions,
may have different elaboration results in different scopes.
Handle those cases in the elaboration caches.
When the clock enable is not generated, don't try to hook it
up then detach it. That will make a mess that needs clean up.
Instead, leave unused ce pins (Enable) unconnected.
Signals are collected in a link map that uses the Link class so that
it doesn't need to save Nexus objects. But naked uses of Link don't
set the node_ and pin_zero_ members. So initialize them to zero so
that Nexus scanners can skip these naked Links.
If statements within blocks can confuse the synthesizer when there
are outputs that are assigned ahead of the if statement. This patch
handles that case.
Martin Whitaker
Martin Whitaker
Johann Klammer
Larry Doolittle
Cary R
Stephen Williams