Now that NetNet objects in NetScopes are kept in a map, remove the
linked list for scanning them. This improves the lookup process from
an O(e**N) process to more like O(log(N)). This matters for very
large designs.
Get at least basic elaboration of analog processes and contribution
statements. Bring the statements and analog statements together and
net future elaboration work sort out which statements are valid in
a given context. This makes sense because there really is a lot of
syntactic overlap, and analog behavioral code is processed somewhat
sequentially.
Put together the infrastructure for elaborating analog statements,
including create the NetAnalogTop objects that hold analog statements
and are in turn held by the design.
While doing this, clean up the various unique initial/always enumerations
to use the ivl_process_type_t type.
The optimization that allowed a mux that had one input always
connected to high-Z produces code that is actually slower than
the original mux, so for now we are removing that optimization.
Continue cleaning up shadowed variables, flagged by turning on -Wshadow.
No intended change in functionality. Patch looks right, and is tested
to compile and run on my machine. No regressions in test suite.
The bufif devices do not correctly propagate the Z value as
required by the standard. The MOS devices do propagate a Z
value, but they do not correctly handle the case where both
inputs are Z and the select is undefined/Z. The standard
specifies that this should be X, but we produce Z. The full
MUX and %blend operator also function this way, so Icarus
may not match the standard, but it is consistent. I would
also argue that the standard is incorrect. If both inputs
are Z then the output should be Z no matter what select is.
The condition expression needs its width tested, even if the width
is not used. Also clean up some handling of widths/types for other
expression types.
This fixes the sign calculation for port padding. It also reports if
the padding will be signed or not in the warning message. The inout
calculation may not be correct. It requires both the signal and the
port to be signed, but inout is not currently padded anyway.
If a part select (either a constant or constant indexed part select)
of a L-value is fully outside the signal the part select will be
omitted after printing a warning. If a part select straddles the
upper portion of a signal a warning will be printed. The run time
will use only the appropriate part of the select. Straddling the
lower part of the signal is not currently supported and a message
is printed for this case.
The right-operand of shift expressions is self-determined, but we still
need to run a test_width to get the PExpr decorated with types and
expression widths.
A casex statement cannot be directly translated to a VHDL case
statement as VHDL does not treat the don't-care bit as special.
The solution here is to generate an if statement from the casex
which compares only the non-don't-care bit positions.
The l-value doesn't really constrain the size of unsized expressions
because there are possible sub-expressions that may pull high bits
down to the low bits. (Divide, for example.)
It is possible, via the use of the $signed() function, for concatenation
expressions to be signed. Make sure the evaluated constant had the
proper sign by checking explicitly.
Continue cleaning up shadowed variables, flagged by turning on -Wshadow.
No intended change in functionality. Patch looks right, and is tested
to compile and run on my machine. No regressions in test suite.
This patch modifies the code that finds and combines similar events
such that if similar events are found in both static and automatic
scopes, the retained event will be in a static scope. This is a
performance enhancement, as VVP has more run-time overhead when
handling events declared in an automatic scope.
This code was likely never checked properly since it makes no
sense to copy the expression from the new temporary system
function. You must copy the value from the current function.
Even on 64 bit machines immediate values should be limited to
32 bits so that the a.out file will run correctly on a 32 bit
machine. This patch fixes a number of places where the code
generator was not checking for/observing this.
The signedness of comparison expressions is typically unsigned, even if
the comparison to be performed is signed. The comparison (and particularly
the expr_synth of the comparison) needs to account for this explicitly.
If either of the operands of a ternary expression are unsigned, then
both are treated as unsigned. It works just like a binary expression
in that regard.
It is up to the elaborator to sign-extend the inputs if the multiply
is signed in the Verilog source. The run time always processes the
multiply as unsigned.
The results of comparisons are unsigned, but the arguments may be signed
and the calculation performed may be signed. Handle the padding properly
for comparisons so that the math is properly signed.
When doing lossless addition to an unsized constant, we make the size
be width of an integer, only to be consistent with other tools. In fact,
don't go overboard if we don't have to.
Later passes need the intermediate results for width and size so that
some special cases, were self-determined arguments occur, can be
processed properly during elaboration. This can be especially tricky
and interesting for ternary expressions.
Start cleaning up shadowed variables, flagged by turning on -Wshadow.
No intended change in functionality. Patch looks right, and is tested
to compile and run on my machine. YMMV.
This patch fixes the expression width calculation for a multiply
operation with an unsized operation. The expression width needs
to be at least the minimum of the maximum multiply result width
and the width of an integer.
Currently, a bitwise boolean operator will cause the expression
width to be reduced to the size of the result. This can give
rise to incorrect results. This patch changes the behaviour to
take into account the required precision for calculating the
two operands.
This patch removes all the checks for constant expressions performed
during the parsing phase, as these checks are (mostly) repeated during
elaboration. It adds the missing check in the elaboration phase (the
RHS of a register initialisation), and improves the error reporting
and error recovery in other checks.
This patch fixes pr2132552, which was caused by a fault in the parser
constant expression checking.
Emitting a VHDL expression like Resize("01", 32) is ambiguous
between interpreting "01" as a Signed or an Unsigned. There's
no point actually outputting this as we can sign-extend the
constant value in the code generator, which is what this
patch does.
In assignments, the expression width may be defined by the width of
operands, and not that of the l-value. Choose whichever is creater and
set (or pad) the expression to that width.
Stephen Williams
Nick Gasson
Cary R
Larry Doolittle
Martin Whitaker