Commit Graph

622 Commits

Author SHA1 Message Date
Henry Wong f827e4f748 Pop current_block_stack after for_variable_declaration and foreach. 2016-10-27 10:29:18 -07:00
Martin Whitaker 3c9b39846c Use gn_system_verilog() where appropriate.
Replace explicit comparisons against generation_flag with calls to
the gn_system_verilog helper function, both for code clarity and
to fix a couple of bugs. Also simplify the implementation of the
function, as we already rely on the generation_flag enumeration
being an ordered list.
2016-09-08 23:00:48 +01:00
Martin Whitaker ad87704809 Partial fix for br1006 - allow part selects in path declarations.
This just enables the compiler to parse path declarations that
contain part selects. As for bit selects, the part select is
discarded, and if elaboration of specify blocks is enabled,
the path declaration will be applied to the entire vector. If
elaboration is enabled, a warning message will now be output
when a bit or part select is discarded.
2016-07-10 20:00:39 +01:00
Cary R 45fbf55806 Add basic support for parameters using typedefs 2016-05-14 10:34:50 -07:00
Martin Whitaker 6ba2bee977 Fix for br974 - support SV types in non-ansi port declarations. 2016-04-04 20:40:30 +01:00
Martin Whitaker dc1c3a4043 Fix for GitHub issue #94 - enhance support for SystemVerilog size casting.
Allow the size expression to be any constant expression. Also ensure that
the expression width and type are correctly calculated and applied.
2016-03-25 21:49:28 +00:00
Martin Whitaker 9538c81d34 Add check for explicit lifetime when initialising static variables.
If a static variable declared in a task, function, or block has an
initialisation expression, SystemVerilog requires the declaration to
have an explicit static lifetime. This is supposed to be a compile
error, but for now just output a warning.

Implementing this required adding support in the parser for explicit
lifetimes in variable declarations. For now, just output an error if
the user asks for a lifetime that isn't the default for that scope.
2016-03-19 20:44:36 +00:00
Martin Whitaker 6e718c2e0c Added support for default subroutine lifetimes (SystemVerilog). 2016-03-19 17:27:27 +00:00
Martin Whitaker 635adfc01e Fully support variable initialization in tasks/functions/named blocks. 2016-03-19 13:04:38 +00:00
Stephen Williams 9a7f31c728 Functions that return strings pass the return value on the stack. 2016-03-01 15:38:28 -08:00
Martin Whitaker e98bcb61bb Fix for br988 - support begin/end blocks nested inside generate blocks.
This is syntax permitted in 1364-2001 but removed in 1364-2005.

Also update the iverilog man page to document the anachronisms warning
class that warns about use of this feature when a later generation is
selected.
2015-08-07 22:46:09 +01:00
Martin Whitaker 853f119d83 Fix for br989 - unsupported attributes are not fatal.
The compiler was emitting a "sorry" message and aborting compilation when
it encountered attributes on a wire declaration/assignment. Change this
to a warning, as most attributes are ignored anyway.
2015-08-05 18:22:25 +01:00
Maciej Suminski 311ffb27f2 ivl: Enum output ports are implicit regs when based on 'logic' type. 2015-06-24 23:53:33 +02:00
Martin Whitaker bdd0657140 Reject default task/function arguments when parsing traditional Verilog. 2015-06-21 09:05:39 +01:00
Larry Doolittle b23faff27c Just a few more spelling fixes
Includes some user-visible messages
2015-06-17 08:09:34 -07:00
Maciej Suminski 80403d2ade ivl: Disabled reg_flag for time type in SV. 2015-06-08 18:42:52 +02:00
Maciej Suminski cd3180d1c2 ivl: TIME_LITERAL added as a primary expression. 2015-06-08 18:42:52 +02:00
Martin Whitaker 71b1546a7d Fail gracefully when an unpacked struct is declared. 2015-05-17 21:59:05 +01:00
Martin Whitaker 352175d921 Fix for br973 - add support for enum declarations with no dimensions. 2015-04-26 12:46:08 +01:00
Larry Doolittle 5dc1396eea Spelling fixes 2015-04-13 11:35:12 -07:00
Cary R 21c60b38e1 Fix space issues in the code. 2015-01-15 17:47:39 -08:00
Maciej Suminski b6e16aea6b ivl: Typedefs may use unpacked arrays. 2015-01-12 11:08:31 +01:00
Cary R 3f847fd927 Fix a compile warning 2015-01-10 16:28:55 -08:00
Martin Whitaker bca84d9dbb Added parser support for SV modport declarations. 2015-01-10 11:10:41 +00:00
Martin Whitaker b400532169 Added support for interface declaration and instantiation.
modport and extern tf declarations are not yet supported.
2014-12-19 23:10:14 +00:00
Martin Whitaker 6aa8e49b09 Add sorry message for unsupported arrays of named events. 2014-12-13 17:46:56 +00:00
Maciej Suminski daa59a95ad ivl: Parsing rules for type casting. 2014-11-27 17:36:23 +01:00
Cary R cd992b4d5a Add file/line information for parray data type. 2014-11-24 18:37:40 -08:00
Cary R c25538d750 Pass the integer type for enumerations to the IVL target stage 2014-10-31 18:09:19 -07:00
Stephen Williams bfafd175fa Fix parse.y bad handling of file names in some situations.
The YYLLOC_DEFAULT() macro needs to get the .text value even
when the rules are empty.
2014-10-02 19:42:48 -07:00
Cary R d16a9dcfc6 Add support for calling a class function method using this/super
Also standardize the parser code that uses this/super.
2014-09-16 12:25:14 -07:00
Cary R acce9fc2a0 Report that external class methods/constructors are not supported 2014-09-11 16:35:24 -07:00
Stephen Williams 853512868b Merge branch 'x-mil15' 2014-09-08 21:10:14 -07:00
Cary R 9b1de4b038 Call IEEE 1800 SystemVerilog 2014-09-08 20:49:40 -07:00
Cary R ec2793c9b0 Warn that classes defined in the compilation unit scope are not supported 2014-09-08 16:59:18 -07:00
Stephen Williams d1a35d5152 Handle nil queue as a was to delete a queue.
Treat this like assigning null to a dynamic array. This deletes the
queue and thus has the effect of clearing it.
2014-09-02 12:19:58 -07:00
Stephen Williams f602ae84ab Elaborate foreach loops as synthetic for loops.
Create an implicit scope to hold the index variable, and
generate a for loop to perform the functionality of the
foreach.
2014-08-21 16:44:46 -07:00
Stephen Williams 6d052d4ff7 Handle queue types and expressions at pform level. 2014-08-21 16:44:45 -07:00
Stephen Williams 2d2a720ea8 Do a better job with synthesis translate pragmas. 2014-08-09 08:04:25 -07:00
Cary R 0cbd6d99af SV: Add support for var decls in unnamed fork/join* blocks.
SystemVerilog allows variables to be declared in unnamed fork/join*
blocks. This patch adds support for this functionality.
2014-07-23 09:54:19 -07:00
Cary R 8e7e3c7493 Remove space issue 2014-07-22 18:59:58 -07:00
Cary R 588409389e SV: Add support for var decls in unnamed begin/end blocks.
SystemVerilog allows variables to be declared in unnamed begin/end
blocks. This patch adds support for this functionality.
2014-07-22 18:58:23 -07:00
Stephen Williams 14f597acdd Add support for synthesis translate meta-comments. 2014-07-15 18:03:40 -07:00
Cary R 0611135758 Some more cppcheck cleanup/updates 2014-06-29 20:39:40 -07:00
Cary R 734d56ce25 Remove space issue. 2014-04-10 14:37:07 -07:00
Stephen Williams c8b20da4be Merge pull request #21 from toddstrader/master
package imports in module headers
2014-04-07 14:09:50 -07:00
Stephen Williams e55e832ea0 Handle unpacked arrays as output ports. 2014-04-06 08:40:09 -07:00
Stephen Williams 6caa41cc93 First pass at support for continuous assign of unpacked net arrays. 2014-04-06 08:40:09 -07:00
Stephen Williams f8e33b12cd Clean up pform_module_define_port in preparation for new tricks.
Get rid of the data_type, signed_flag, and range arguments to the
pform_module_define_port because they add no value within the
parse.y parser. Cleaning these out will hopefully ease the addition
of new functionality.
2014-04-06 08:40:09 -07:00
Stephen Williams aaee9989c2 Handle for_variable_declaration
This can be handled entirely in the parser, where we rewrite the
syntax to me a begin/end block that contains the index variable
declaration and the for loop.
2014-04-06 08:40:08 -07:00
Stephen Williams a849249a86 Allow typedefs to override inherited type names. 2014-04-06 08:40:08 -07:00
Todd Strader (todd.strader@gmail.com) 849ba64cf7 package imports in module headers
See IEEE 1800-2012 A.1.2 module_nonansi_header and module_ansi_header
2014-04-03 20:11:57 -04:00
Martin Whitaker a3450bf856 Fixes for GitHub issues 13 and 15.
The verinum arithmetic operators now observe the standard Verilog
rules for calculating the result width if all operands are sized.
If any operand is unsized, the result is lossless, as before.
They also now all observe the standard rules for handling partially
undefined operands (if any operand bit is 'x', the entire result is
'x').

I've also added the unary '-' operator, and renamed v_not() to be
the unary '~' operator. This has allowed some simplification in
other parts of the compiler.
2014-02-25 20:39:21 +00:00
Stephen Williams 830083d99b Merge branch 'x-sizer3' 2014-02-16 17:05:53 -08:00
Stephen Williams 6902bf44e3 Improved error handling in parser around typedefs. 2014-02-16 17:04:52 -08:00
Stephen Williams 8f849a9944 Sorry message for unpacked array module ports. 2014-02-16 15:56:32 -08:00
Martin Whitaker 8135f369a5 Fix for GitHub issue 11 : Syntax error on operator attributes.
Attributes are allowed to be attached to unary, binary, and ternary
operators in expressions. For now just accept and discard them.
2014-02-14 23:29:22 +00:00
Stephen Williams 52a9fdde8a Handle packed structs as module outputs. 2014-02-03 19:22:59 -08:00
Stephen Williams 49cf5556a2 Fix primitive table lexical analysis.
Sequences of digits in the table of a primitive may be matched
as decimal numbers instead of digits, and this breaks some
primitives.
2014-02-02 10:57:53 -08:00
Stephen Williams 8a4d769b3d Type name expressions down to elaboration. 2014-01-11 19:19:15 -08:00
Stephen Williams b0491b9c54 Handle typedefs in $root scope. 2014-01-11 19:19:14 -08:00
Stephen Williams 7669a42cfb Handle some assertion syntax in the parser.
Implement some yacc rules for assertion syntax.

Add the -gassertions/-gno-assertions command-line flags to
enable or disable assertions.
2013-12-07 12:20:28 -08:00
Stephen Williams 49756a8e7a Unions through pform. 2013-12-07 12:20:28 -08:00
Stephen Williams be7d763352 Sorry message for union declarations. 2013-11-22 10:39:48 -08:00
Stephen Williams 0692cd54e7 Support some simple class initialization assignments. 2013-11-16 17:04:14 -08:00
Stephen Williams 9bd9c8f301 Implement class extends arguments.
This implements constructor arguments right after the base class
name in the class extends syntax.
2013-11-10 18:03:19 -08:00
Stephen Williams d192f545ac Chain class instance constructors with arguments. 2013-11-10 18:03:19 -08:00
Stephen Williams 9f83882bcc Parse/elaborate class derivation
This gets us down to working classes, but does not yet implement
calls to the parent constructor, implicitly or explicitly.
2013-11-10 18:03:19 -08:00
Cary R 97d06b107f Add support for wait fork to the compiler and code generators 2013-10-22 09:41:03 -07:00
Stephen Williams 2030e06988 Parse/elaborate some array-patterns down to the ivl_target API. 2013-10-19 15:34:14 -07:00
Stephen Williams 18c338ad09 Handle array assignment patters through pform.
This gets us to elaboration. In the process also fix up ivl_type_t
type comparisons to do deep type comparison.
2013-10-19 15:34:14 -07:00
Stephen Williams 5494c9ae09 Support DARRAY objects as port arguments. 2013-10-19 15:34:14 -07:00
Cary R c64b8900ca Add support for disable fork to the compiler. 2013-10-17 19:34:57 -07:00
Stephen Williams a9a1c50268 Support "this" for calling task methods. 2013-09-20 20:44:57 -07:00
Stephen Williams 5084a23417 Sorry messages for calls to superclass constructor. 2013-09-20 20:44:57 -07:00
Stephen Williams 46f551073e Handle default expressions anywhere in port expression list. 2013-09-20 20:44:57 -07:00
Stephen Williams 9a116498a2 Handle task/function default expressions in parsing/pform.
This gets it to (but not through) the elaborator.
2013-09-20 20:44:56 -07:00
Cary R d8f945be23 Add support for SV do/while 2013-09-16 20:02:09 -07:00
Stephen Williams 173577d5f7 Merge branch 'work14' 2013-07-03 20:00:22 -07:00
Stephen Williams 4ef3ac5ca6 Implement const properties of classes.
This implementation works by detecting assignments
to constant properties in elaboration. Allow initializer
assignments to assign to the constant, error all other
assignments, and otherwise treat the constant like any
other property.
2013-07-02 20:16:47 -07:00
Stephen Williams cf47a759d1 Implement the "local" class member protection.
Test during elaboration that the member really is
accessible in the context where the elaboration
happens.
2013-07-02 20:16:47 -07:00
Stephen Williams fbc5557a10 Handle properties that have arbitrary bit widths.
This fixes the run time handling of arbitrary width
bit vectors as class properties. The vvp code generator
already did the right things.
2013-07-02 20:16:47 -07:00
Stephen Williams 75b4b94061 Elaborate implicit initializers
Remaining pform fixup of property initializers, and
elaboration and code generation for implicit constructor.
2013-07-02 20:16:46 -07:00
Cary R 11e5641089 A real task/function port is also signed. 2013-06-27 13:03:11 -07:00
Stephen Williams 1b178d56b7 Add support for SystemVerilog return statements. 2013-06-12 14:09:07 -07:00
Martin Whitaker 6364aba975 Fix for br930 - support attributes on old-style port declarations. 2013-05-19 09:16:24 +01:00
Cary R 71c6193ff1 Finish adding support for end labels in SystemVerilog 2013-05-14 15:01:54 -07:00
Cary R 7c1638652a Add support for closing a procedural begin/fork block with a name 2013-05-08 18:34:16 -07:00
Cary R 51d3c03922 A time variable is always unsigned and pass the integer property 2013-04-30 14:05:19 -07:00
Stephen Williams eff6e7a441 Parse to pform shallow copy "new" expressions. 2013-04-21 19:27:57 -07:00
Stephen Williams 8994ef1483 Implement class constructors.
Class constructors are the "new" method in a class description.
Elaborate the constructor as an ordinary method, but the only
way to access this method is to implicitly call it. The elaborator
will take the constructor call and generate a naked "new" expression
and implicit constructor method call with the object itself as the
return value.
2013-04-20 16:38:35 -07:00
Stephen Williams 20ee350601 Generalize user defined function return type handling.
I'm gonna need functions to return class objects, so generalize
the output types of user defined functions.
2013-04-20 16:38:35 -07:00
Stephen Williams 632fd006c5 Merge branch 'master' of github.com:steveicarus/iverilog 2013-04-16 16:56:14 -07:00
Cary R f536a43e92 Add support for timeunit <time_val> / <time_val> 2013-04-16 14:40:35 -07:00
Stephen Williams 4dffd97d28 Handle tasks in packages. 2013-04-08 18:20:39 -07:00
Stephen Williams eba3d407ca packages can contain variables. 2013-04-08 18:20:39 -07:00
Stephen Williams bae0f1d3a7 Parse more package items
Rework lexical support for PACKAGE_IDENTIFIER so that the lexor
can help with package scoped identifiers.

Pform package types and package functions up to elaboration.
2013-04-08 18:20:39 -07:00
Cary R bdfd5b9b55 Add -g2012 flag and keywords for IEEE 1800-2012. 2013-04-02 14:41:44 -07:00
Stephen Williams 17330a3073 Elaborate class task and function methods.
The parse of class methods already works, this patch forms
the methods into their own scopes, and elaborates those scopes.
The "this"
2013-03-24 15:12:35 -07:00
Stephen Williams fac5cbca43 Handle this as special identifier strings. / Organize pform class member binding 2013-03-24 15:03:52 -07:00