Resolves#328
Summary:
- By default emit Verilog-2001 style module declarations with direction
and signal type defined in the module prototype and not in the body of
the module
- Add -C option to output Verilog-1995 module declarations for
compatibility with older toolchains
- Add some comments to the file to assist future maintainers
Background:
Currently, icebox_vlog outputs a mixed-style module declaration in which
it puts the port direction in the module prototype and later declares
the signals as ports or wires.
```verilog
module chip (input pin1, output pin2);
wire pin1;
reg pin2 = 0;
```
The inclusion of the direction in the module prototype is a feature of
newer Verilog-2001 specification.
It seems probable that older versions of Icarus Verilog had some leeway
in handling this mixed-style of declaration. But, it seems that at least
the version included in newer Ubuntu distributions considers this to be
a syntax error.
In this commit, the module declaration above will be emitted as:
```verilog
module chip (input wire pin1, output reg pin2 = 0);
```
Or if you sepcificy the -C option for Verilog-1995 compatibility:
```verilog
module chip (pin1, pin2);
input pin1;
output pin2;
wire pin1;
reg pin2 = 0;
```
The Lattice tools use these additional commands to read-back the BRAM
and CRAM after programming to validate that it was written correctly.
`iceprog` doesn't use this right now, so this is just for documentation
purposes.
Signed-off-by: Trammell Hudson <hudson@trmm.net>
It's hard to cover 100% of cases, but this seems to improve
probability that a reset works, at least for me on the icebreaker.
Some other flash have a different QPI disable command though :/
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
This is useful when testing litex SoC that rely on that bit being set
The setting is non-volatile so it only needs to be done once in case
you happen to have used a flash chip that's not by default QE=1
(This has been designed for winbond flash. Others might use
different bit ...)
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
When a clock is applied to a dedicated clock pin, SB_PLL40_CORE is no longer the correct primitive to use.
Also the name of the clock input must be PACKAGEPIN (rather than REFERENCECLK)
Chris Baker
myrtle
Catherine
Sylvain Munaut
Tom Verbeure
Aki Van Ness
Miodrag Milanović
Rafael Lee
Maik Merten
Trammell Hudson
Will Green
Claire Xen
Jon Kivinen
David Williams
Piotr Esden-Tempski
David Shah
Nils Albartus
Claire Wolf