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Merge pull request #313 from YosysHQ/gatecat/bram-doc-update 

Update BRAM NegClk info based on latest testing
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myrtle 2023-12-12 13:01:19 +01:00 committed by GitHub
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docs/ram_tile.html
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@ -91,8 +91,8 @@ The read/write mode selects the width of the read/write port:
</table>
<p>
The <span style="font-family:monospace">NegClk</span> bit in the RAMB tile negates the polarity of the <span style="font-family:monospace">WCLK</span> port,
and the <span style="font-family:monospace">NegClk</span> bit in the RAMT tile negates the polarity of the <span style="font-family:monospace">RCLK</span> port.
The <span style="font-family:monospace">NegClk</span> bit in the RAMB tile (1k die) or RAMT tile (other devices) negates the polarity of the <span style="font-family:monospace">WCLK</span> port,
and the <span style="font-family:monospace">NegClk</span> bit in the RAMT (1k die) or RAMB tile (other devices) tile negates the polarity of the <span style="font-family:monospace">RCLK</span> port.
</p>
<p>