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Update BRAM NegClk info based on latest testing 

Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2023-03-20 09:12:23 +01:00
parent d20a5e9001
commit cfc6e9fdf7
1 changed files with 2 additions and 2 deletions
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docs/ram_tile.html
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@ -91,8 +91,8 @@ The read/write mode selects the width of the read/write port:
</table>
<p>
The <span style="font-family:monospace">NegClk</span> bit in the RAMB tile negates the polarity of the <span style="font-family:monospace">WCLK</span> port,
and the <span style="font-family:monospace">NegClk</span> bit in the RAMT tile negates the polarity of the <span style="font-family:monospace">RCLK</span> port.
The <span style="font-family:monospace">NegClk</span> bit in the RAMB tile (1k die) or RAMT tile (other devices) negates the polarity of the <span style="font-family:monospace">WCLK</span> port,
and the <span style="font-family:monospace">NegClk</span> bit in the RAMT (1k die) or RAMB tile (other devices) tile negates the polarity of the <span style="font-family:monospace">RCLK</span> port.
</p>
<p>