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5830 Commits

Author SHA1 Message Date
Alan Mishchenko f1eebf78f4 Updating command "runscript". 2025-07-08 19:06:04 -07:00
alanminko 0dc5524b80
Merge pull request #425 from MyskYko/fix3 
fix cadical
 2025-07-07 03:44:24 -07:00
MyskYko 13205ccbb3 qbf with cadical 2025-06-21 01:29:26 -07:00
MyskYko 5e03f9fefa more APIs in cadical 2025-06-20 15:55:31 -07:00
MyskYko 6e130c15a3 fix setnvars 2025-06-20 15:28:27 -07:00
MyskYko 9ea1aaa3cf fix comments 2025-06-20 14:45:50 -07:00
MyskYko a5156f257e fix cadical 2025-06-20 13:40:04 -07:00
Alan Mishchenko beff7f1b34 Temporary fix of the compilation problem related to sorting objects by level in rewiring. 2025-06-19 14:32:10 +07:00
alanminko 83824878e3
Merge pull request #422 from MyskYko/fix 
fix amap -m
 2025-06-17 21:20:28 -07:00
MyskYko e9845e534a fix a bug when yosys constants are already declared 2025-06-17 16:41:43 -07:00
MyskYko f443db4a24 fix amap -m 2025-06-16 10:27:33 -07:00
Alan Mishchenko 6463f11625 Fixing pointer-dependent behavior during BDD variable reordering. 2025-06-07 12:52:23 -07:00
alanminko afae379366
Merge pull request #419 from mikesinouye/multilib 
Prevent merged scl filename size from growing unbounded.
 2025-06-07 10:38:15 -07:00
alanminko 5cf5a8d9f5
Merge pull request #412 from tklam/feature/support_verilog_gate_name 
Support primitive gates with names in Verilog netlist
 2025-06-07 10:38:03 -07:00
Mike Inouye a4064b8b73 Prevent merged scl filename size from growing unbounded, which limits upper bound of files loaded. 2025-05-30 18:14:47 +00:00
alanminko 0a55186553
Merge pull request #416 from chenjunhao0315/master 
patch rewire with empty name
 2025-05-25 22:27:43 -07:00
Alan Mishchenko 1f98c28011 Improved cascade printout in "lutcasdec". 2025-05-25 22:24:33 -07:00
Alan Mishchenko 301b46e3c1 Fixiing BLIF reader to read Yosys constants. 2025-05-25 18:45:59 -07:00
jiunhaochen 04161dfda8 patch rewire with empty name 2025-05-26 01:44:04 +08:00
Alan Mishchenko 0ae04514cd Work-around for a bug in "lutcasdec". 2025-05-22 23:56:40 -07:00
Alan Mishchenko 716314d835 Generating AIGs for adders. 2025-05-22 23:56:13 -07:00
Alan Mishchenko 32fe49b6d1 New commands for reading/writing mini-mapping for AIGs. 2025-05-21 21:57:51 -07:00
Alan Mishchenko e1a1994292 Extending "&cofs" to handle multi-output AIGs. 2025-05-21 21:30:58 -07:00
alanminko 0c155952bf
Merge pull request #415 from HAHHHD/master 
add clause pushing with blocking
 2025-05-20 16:37:20 -07:00
Alan Mishchenko 3bd7bac552 Improvements to "lutcasdec". 2025-05-20 16:17:43 -07:00
HAHHHD e20c484ee1 add clause pushing with blocking 2025-05-20 15:04:15 -07:00
Alan Mishchenko c5edc566ff Improvements to "lutcasdec". 2025-05-20 14:28:07 -07:00
Alan Mishchenko 29c8d3eacf Improvements to "lutcasdec". 2025-05-20 10:41:47 -07:00
Alan Mishchenko 9bb736acee Improvements to "lutcasdec". 2025-05-20 06:39:28 -07:00
Alan Mishchenko c398b06740 Experiments with decomposition. 2025-05-20 06:08:46 -07:00
Alan Mishchenko 240bf58f90 Updating "short_names" and BDD profiling. 2025-05-19 10:24:56 -07:00
Alan Mishchenko 916f70058e Updating script runner. 2025-05-18 14:05:50 -07:00
Alan Mishchenko 0b1d7c6d0f Supporting structural choices in rewiring. 2025-05-18 13:37:30 -07:00
Alan Mishchenko 5daa0c347e Small changes to "lutcasdec". 2025-05-16 17:23:32 -07:00
Alan Mishchenko 57966de4b4 Adding flag to skip two-output cells in "read_lib". 2025-05-14 17:01:48 -07:00
Alan Mishchenko d34821e768 Skipping cells with more than two outputs in "read_lib". 2025-05-14 14:17:05 -07:00
Alan Mishchenko 078debff4e Adding print-out of LUT mapping stats. 2025-05-13 22:49:55 -07:00
Alan Mishchenko d245305393 Improvements to "lutcasdec". 2025-05-13 19:21:56 -07:00
tklam 9545b79e0e support primitive gates with names in Verilog netlist 2025-05-12 10:20:13 -04:00
Alan Mishchenko c85f007f75 Convert buffers to .short lines in BLIF. 2025-05-09 18:16:37 -07:00
Alan Mishchenko 490bb92a8c Fixing the Yosys script used to read a mapped netlist. 2025-05-09 17:17:26 -07:00
Alan Mishchenko a42e6ecd23 Fixing a bug in "read_lib". 2025-05-09 17:13:40 -07:00
Alan Mishchenko 9dc7ade063 Adding a switch to read mapped Verilog using command %yosys. 2025-05-09 11:47:26 -07:00
Alan Mishchenko 71b60a9830 Updating &stochsyn. 2025-05-07 19:53:53 -07:00
Alan Mishchenko 4560597b31 Utility to duplicate inputs. 2025-05-07 16:53:51 -07:00
Alan Mishchenko 49d9252f90 Updating the way min col mult is reported in lutcasdec. 2025-05-05 09:03:41 -07:00
Alan Mishchenko 5e54ef3aff Adding printout of flops. 2025-05-03 18:15:11 -07:00
Alan Mishchenko f9e4d06806 Column multiplicity statistics 2025-05-02 08:18:12 -07:00
Alan Mishchenko 692b0c6908 Printout of column multiplicity statistics. 2025-05-02 08:13:20 -07:00
Alan Mishchenko 75adf123f6 Adding new feature to &nf. 2025-05-01 22:41:49 -07:00
Alan Mishchenko 1c2b935a77 Adding new feature to "lutexact". 2025-05-01 21:08:46 -07:00
Alan Mishchenko 391a767c16 Updating LUT cascade mapping. 2025-05-01 11:51:48 -07:00
Alan Mishchenko 6a031620fe Supporting random seed in "lutexact". 2025-04-30 12:10:22 -07:00
Alan Mishchenko 59bb4de39f Misc changes. 2025-04-30 10:47:12 -07:00
alanminko 5305d93037
Merge pull request #405 from MyskYko/rrr 
update rrr
 2025-04-25 06:48:30 +07:00
jiunhaochen b1734ac297 rewire clean up 2025-04-19 00:43:48 +08:00
MyskYko b1b1023285 update rrr 2025-04-17 11:01:39 -07:00
jiunhaochen 0ab176d7c9 rewire fix genlib change 2025-04-17 16:14:49 +08:00
jiunhaochen 01bfd8fbad rewire fix not mapped 2025-04-17 12:39:24 +08:00
Alan Mishchenko 3a063c5901 Allowing more aggressive restructuring in "stochmap". 2025-04-16 16:58:04 -07:00
Alan Mishchenko 1626a337a1 Adding random seed to "lutcasdec". 2025-04-16 16:35:23 -07:00
jiunhaochen 6c37cc9ac3 rewire restructured even if the cost is not improved 2025-04-17 04:58:32 +08:00
Alan Mishchenko dcf9079507 Extending "stochmap" to work for AIGs. 2025-04-15 21:56:24 -07:00
Alan Mishchenko 47ac9f75ca New command "&andcare" to AND the miter with the careset. 2025-04-15 20:00:19 -07:00
Alan Mishchenko 1a1bdbe4c8 Another typo. 2025-04-10 07:03:19 -07:00
jiunhaochen 2179034f23 command rewire fix condition 2025-04-10 17:24:27 +08:00
jiunhaochen 43d12f6c31 command rewire add external careset 2025-04-10 16:57:13 +08:00
Chen jiun hao 08ccd6d0b9
Merge branch 'berkeley-abc:master' into master 2025-04-10 16:52:03 +08:00
Alan Mishchenko d271403514 Fixing a typo. 2025-04-09 21:23:44 -07:00
Alan Mishchenko c5fdfb3835 New command "runscript". 2025-04-09 18:16:24 -07:00
Alan Mishchenko 83150e6549 Enable overlapping partitions in "stochmap". 2025-04-09 08:46:38 -07:00
jiunhaochen 5700bff205 command rewire add external care 2025-04-09 19:27:32 +08:00
alanminko 68c576cc56
Merge pull request #400 from MyskYko/rrr 
update rrr
 2025-04-07 11:34:13 +07:00
Alan Mishchenko 3846c193f2 Enable overlapping partitions in "stochmap". 2025-04-06 17:01:40 -07:00
MyskYko 27f2429d76 update rrr 2025-04-06 15:46:02 -07:00
Alan Mishchenko c0be439b45 Performance improvements. 2025-04-06 00:14:02 -07:00
Alan Mishchenko 1b6b553922 New commands for truth table file processing. 2025-04-05 22:40:24 -07:00
Alan Mishchenko 3f479dc84f Bug fixes in LUT cascade. 2025-04-05 22:39:59 -07:00
Alan Mishchenko 5c604949af Enable dumping of the resulting permutation of internal nodes in "permute". 2025-04-05 16:37:49 -07:00
Alan Mishchenko 96c28881a8 Bug fix in LUT cascade. 2025-04-01 19:03:17 -07:00
alanminko e3b96c784f
Merge pull request #396 from fxreichl/master 
Extend logging for eSLIM
 2025-04-01 20:35:49 +07:00
alanminko a4d6775b7c
Merge pull request #384 from QiuYitai/master 
Fix the null reference vulnerability
 2025-04-01 20:35:09 +07:00
Franz Reichl 2c003f8865 Extend logging for eSLIM 2025-04-01 11:50:28 +02:00
Alan Mishchenko 29706ebede Bug with LUT cascade mapping. 2025-03-31 19:09:54 -07:00
Alan Mishchenko 80becaf2e2 Bug fix in LUT cascade decomposition. 2025-03-31 18:33:38 -07:00
Alan Mishchenko 9cdbb79338 Bug fix in handling concurrency in "stochmap". 2025-03-31 15:39:05 -07:00
Alan Mishchenko dc72d1e120 New command &store. 2025-03-31 15:24:15 -07:00
Alan Mishchenko 4656ae10e0 Updates to the GPC-based mapping. 2025-03-30 19:55:07 -07:00
Alan Mishchenko 6d6a5accb4 Experiments with LUT cascade mapping. 2025-03-30 18:20:55 -07:00
Alan Mishchenko 4ac014db41 Experiments with adder mapping. 2025-03-30 09:15:54 -07:00
Alan Mishchenko db2b52ca03 Bug fix. 2025-03-29 16:54:10 -07:00
Alan Mishchenko 2b5f102bdb Updating input file format in command "permute". 2025-03-29 15:48:07 -07:00
Alan Mishchenko bb11cc4c46 Experiments with adder-tree mapping. 2025-03-29 15:37:22 -07:00
Alan Mishchenko 2442720528 Adding counter generation to "symfun". 2025-03-29 11:11:13 -07:00
Alan Mishchenko 938ae9428b Extending interface of "permute". 2025-03-28 18:35:30 -07:00
Alan Mishchenko f5ac2d4bd3 Updates to LUT cascade decomposition. 2025-03-19 12:20:25 -07:00
Alan Mishchenko e320888191 Adding structural guidance. 2025-03-19 12:14:28 -07:00
Franz Reichl 8ffca32372 Add command &eslim 2025-03-19 11:29:14 +01:00
Alan Mishchenko e7dd9151b1 Adding structural guidance. 2025-03-18 17:51:40 -07:00
Alan Mishchenko 2078b3945b Adding support for the random seed to the recent experiments. 2025-03-18 07:55:28 -07:00
Alan Mishchenko 30c952ed22 Remove structural choices after mapping. 2025-03-17 17:17:48 -07:00
Alan Mishchenko 59a7cc5c9c Removing intermediate files in exact synthesis. 2025-03-17 17:12:01 -07:00
Alan Mishchenko e20cbd6120 Updating command "cone" to extract a comma-separated list of outputs. 2025-03-17 16:10:22 -07:00
jiunhaochen e937e82cc6 rewire with &nf, &simap 2025-03-17 10:26:32 +08:00
jiunhaochen c63cf09660 rewire support level constraint 2025-03-17 10:26:32 +08:00
jiunhaochen 67d8095515 fix read_mm 2025-03-17 10:26:32 +08:00
jiunhaochen c3b76b1712 Patch rewire 2025-03-17 10:26:32 +08:00
Alan Mishchenko 0ebc9dbbae Experiments with exact synthesis. 2025-03-16 09:39:04 -07:00
Alan Mishchenko 839f3e18dd Experiments with mapping. 2025-03-14 20:24:08 -07:00
Alan Mishchenko aaba1b9a5f Experiments with mapping. 2025-03-13 20:59:17 -07:00
Alan Mishchenko d55735df2b Updates to the result reporting. 2025-03-13 11:57:53 -07:00
Alan Mishchenko 27fdbe0162 Updates to the mapping experiment. 2025-03-13 11:57:34 -07:00
Alan Mishchenko 2361a02c99 Fixing compilation problemj in some builds. 2025-03-12 20:53:02 -07:00
Alan Mishchenko feefa0f513 Supporting out of order signal names in AIGER reader. 2025-03-12 20:12:28 -07:00
Alan Mishchenko 5ef9c3c50b Experiment with mapping. 2025-03-12 20:11:33 -07:00
qiuweibin 02f3727d87 Fix the null reference vulnerability 2025-03-11 03:38:50 +00:00
Alan Mishchenko b09305204d Minor bug fixes. 2025-03-10 20:13:53 -07:00
Alan Mishchenko 2c45f9dce2 Adding conflict limit and timeout to &simap. 2025-03-10 17:54:30 -07:00
Alan Mishchenko 40ea8a7598 Enabling support for input/output names in mini mapping format. 2025-03-10 17:29:01 -07:00
Alan Mishchenko 9390a74c54 Changes to the file interface in "stochmap". 2025-03-10 14:40:28 -07:00
Alan Mishchenko bd9fb45808 Adding direct file interface for mapped networks. 2025-03-10 14:38:51 -07:00
Alan Mishchenko ecc27e80dc Adding support for the genlib library file name. 2025-03-10 14:37:29 -07:00
Alan Mishchenko 9665696a94 Code refactoring to dump CNF files. 2025-03-10 13:17:04 -07:00
Alan Mishchenko 67fdd8d244 Random crash fix. 2025-03-10 13:06:14 -07:00
Alan Mishchenko 0e117760e2 Performance improvement. 2025-03-10 00:37:51 -07:00
Alan Mishchenko c62bf1b89c Updating cut level. 2025-03-10 00:08:35 -07:00
Alan Mishchenko 3dc77bbe1c Bug fix in "stochmap". 2025-03-09 23:52:03 -07:00
Alan Mishchenko 38ba7d78aa Experiment with mapping. 2025-03-09 15:42:25 -07:00
alanminko f058e15f87
Merge pull request #382 from MyskYko/cadical 
CaDiCaL
 2025-03-07 23:17:57 +07:00
alanminko 383c16b690
Merge pull request #380 from MyskYko/kissat 
support debug mode
 2025-03-07 23:17:44 +07:00
qiuweibin db4a3005e3 Fix the null reference vulnerability 2025-03-07 10:48:02 +00:00
MyskYko 14b451b52f patch 2025-03-07 00:25:11 -08:00
MyskYko f544165a88 cadical original 2025-03-05 21:25:31 -08:00
MyskYko 8fb9fc5d0f add version 2025-03-05 21:19:39 -08:00
MyskYko f168f2f286 support debug mode 2025-03-05 20:25:40 -08:00
alanminko fbd19056e7
Merge pull request #379 from MyskYko/rrr 
update rrr
 2025-03-06 09:00:36 +07:00
Alan Mishchenko 7364002c39 Updates to rewiring. 2025-03-05 17:47:12 -08:00
Alan Mishchenko f3ae349cf2 Bug fixing in "stockmap". 2025-03-05 17:46:39 -08:00
MyskYko 8005405ed7 update rrr 2025-03-05 14:44:12 -08:00
Alan Mishchenko 2126cb3ca1 Fixing a typo in Kissat integration. 2025-03-05 10:30:16 -08:00
Alan Mishchenko b9b8ff47e3 Adding programmable call to Kissat in command &kissat. 2025-03-05 08:26:28 -08:00
MyskYko 3f6171127a add license 2025-03-05 04:21:18 -08:00
MyskYko 664d285fcb patch 2025-03-05 04:10:49 -08:00
MyskYko a7476c65d8 kissat original 2025-03-04 17:39:59 -08:00
Alan Mishchenko c25bf73466 Adding new external APIs. 2025-03-03 19:40:11 -08:00
alanminko 1b96863505
Merge pull request #375 from chenjunhao0315/master 
Command rewire
 2025-03-02 01:27:30 +07:00
alanminko adbeffc145
Merge pull request #374 from wjrforcyber/fix_lib_pointer 
Fix(Pointer): Fix the wrong value passed to size
 2025-03-02 01:27:01 +07:00
alanminko d0d1721bbe
Merge pull request #373 from wjrforcyber/fix_HMetis 
Fix(write_hmetis): Remain the obj number when omitting POs explictly
 2025-03-02 01:26:44 +07:00
jiunhaochen 083d3884dd Command rewire 2025-03-01 23:44:55 +08:00
wjrforcyber 5632bb8892
Fix(Pointer): Fix the wrong value passed to size 
Signed-off-by: wjrforcyber <wjrforcyber@163.com>
 2025-03-01 21:03:51 +08:00
Alan Mishchenko 75ef06017d LUT cascade mapping. 2025-02-27 13:40:11 -08:00
wjrforcyber 6046bbee4e
Update(EmptyLine): Remove empty line between data and comment 
Due to the parsing issue here: https://github.com/kahypar/mt-kahypar/pull/205

Signed-off-by: wjrforcyber <wjrforcyber@163.com>
 2025-02-27 16:42:29 +08:00
wjrforcyber e9c7059274
Fix(write_hmetis): Remain the obj number when omit POs explictly 
Signed-off-by: wjrforcyber <wjrforcyber@163.com>
 2025-02-26 21:36:48 +08:00
Alan Mishchenko 45c250fb5b New command &randsyn (fixing scalability issue). 2025-02-23 15:49:49 -08:00
Alan Mishchenko a9d959acbe Command "stochmap". 2025-02-23 15:47:28 -08:00
Alan Mishchenko c4a10c728e Suggested fix of an overflow in vectors (compiler error). 2025-02-23 15:47:00 -08:00
Alan Mishchenko 4f1b961d00 Suggested fix of an overflow in vectors. 2025-02-23 13:17:51 -08:00
Alan Mishchenko 9e35825e6b New command &randsyn. 2025-02-21 13:20:15 -08:00
Alan Mishchenko e5e1f76b21 Bug fix. 2025-02-14 14:41:01 -08:00
alanminko 0cbc9a851a
Merge pull request #368 from hriener/dau_fix 
Increase buffer size to DAU_MAX_STR (=2000).
 2025-02-15 05:30:48 +07:00
alanminko 57e504db7b
Merge pull request #362 from wjrforcyber/gz_lib_support 
Feat(read_lib): Gz lib format support
 2025-02-15 05:30:24 +07:00
alanminko ee8e0370d5
Merge pull request #361 from letsintegreat/power-aware 
Fix switching bug
 2025-02-15 05:29:55 +07:00
alanminko a2c6cb8fd4
Merge pull request #360 from wjrforcyber/fix_print_mffc 
Fix(print_mffc): Missing condition when single output linked to CO
 2025-02-15 05:29:37 +07:00
alanminko 4b6c35bd4d
Merge pull request #356 from wjrforcyber/choice_bug 
Fix(&dch): choices bugs in &put
 2025-02-15 05:29:14 +07:00
alanminko 8a96d02e33
Merge pull request #354 from wjrforcyber/write_hmetis 
Feat(write_hmetis): Enable hMetis format
 2025-02-15 05:28:50 +07:00
alanminko a2e4c153c9
Merge pull request #255 from phsauter/fix-scl-regression 
Fix Segfault in scl
 2025-02-15 05:28:25 +07:00
Heinz Riener 80eecea409 Increase buffer size to DAU_MAX_STR (=2000). 2025-02-14 15:49:17 +01:00
alanminko 7bd782382e
Merge pull request #367 from MyskYko/rrr 
New implementation
 2025-02-14 06:19:30 +07:00
MyskYko f51543457d change default parameter 2025-02-13 12:40:48 -08:00
Alan Mishchenko 775dee4de9 Fixing timing propagation bug in &nf with boxes. 2025-02-12 18:41:12 -08:00
MyskYko 23c632f113 compilation error 2025-02-12 06:16:09 -08:00
MyskYko b0153e0f57 fix template 2025-02-12 06:16:09 -08:00
MyskYko d1d861f703 fix template 2025-02-12 06:16:09 -08:00
MyskYko 6e3b38c7d3 add rrr 2025-02-12 06:16:02 -08:00
alanminko aa9630e169
Merge pull request #365 from QuantamHD/fix_nf_crash 
nf: Fix assert( pDp->F < FLT_MAX ); in nf
 2025-02-12 08:34:50 +07:00
alanminko c4f8e8e88b
Merge pull request #364 from QuantamHD/fix_mising_return 
Fixes missing return in cec
 2025-02-12 08:34:21 +07:00
Alan Mishchenko b7bf6c20b6 Improvements to LUT cascade mapping. 2025-02-11 17:32:19 -08:00
Ethan Mahintorabi 2227d6d4e7
nf: Fix assert( pDp->F < FLT_MAX ); in nf 
This error was triggered by what appears to be a missing
saturating float check in Nf_ManCutMatchOne. When opened
in the debugger AreaF starts at FLT_MAX and in some cases
can be added to itself which results in +Inf. I noticed the
other if had a  saturating condidtion.

I took a flyer on it, and added it to the previous condition,
and it resolved the error. I think this is a good fix.

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2025-02-11 22:04:24 +00:00
Ethan Mahintorabi 964170d8dc
Fixes missing return in cec 
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2025-02-10 05:44:31 +00:00
Alan Mishchenko 8912d3aabe Adding command &write_truth equivalent to &write_truths. 2025-01-29 17:40:17 -08:00
Alan Mishchenko 3e86444510 Bug fix in reading truth tables. 2025-01-29 17:37:24 -08:00
wjrforcyber 303907ec0c
Update(read_lib): Remove redundant header 2025-01-21 15:58:31 +08:00
wjrforcyber adf9b4e7fb
Feat(read_lib): Support .gz file 2025-01-21 15:54:38 +08:00
letsintegreat a75d0cb0ad
fix switching bug 2025-01-18 22:41:24 +05:30
wjrforcyber 910a66a372
Fix(print_mffc): Missing condition when single output linked to CO 2025-01-17 18:31:14 +08:00
wjrforcyber a03c126a13
Refactor(Redundant): Remove redundant code 2025-01-09 23:39:02 +08:00
wjrforcyber c1ac7d8153
Update(&ps): Revert two line since `cls` shows the same data 2025-01-09 23:04:00 +08:00
wjrforcyber 8c7c9d0ccf
Fix(&dch): choices bugs in &put 2025-01-09 22:21:32 +08:00
Alan Mishchenko d5e1a5d445 Bug fix in &gencex. 2025-01-02 00:33:22 +07:00
Alan Mishchenko 350dcd3ea4 Enabling shared variables in bound set evaluation. 2024-12-28 00:05:00 -08:00
wjrforcyber 71b3daf0f6
Merge remote-tracking branch 'upstream/master' into write_hmetis 2024-12-26 20:58:17 +08:00
Alan Mishchenko b59b475d6a Compiler error. 2024-12-26 00:56:18 -08:00
Alan Mishchenko 7d247a08f7 Experiments with bound-set evaluation. 2024-12-26 00:37:37 -08:00
wjrforcyber 0dff4dbc4b
Feat(write_hmetis): Add weight on hyperedges and format 2024-12-26 13:54:55 +08:00
wjrforcyber 7a5a0ad8b3
Refactor(Compile): For MSVS build 2024-12-26 11:27:24 +08:00
wjrforcyber f7c5241dee
Merge branch 'master' into write_hmetis 2024-12-25 15:54:34 +08:00
wjrforcyber 47e4e23bc5
Fix(write_hmetis): Comments should be start with % 2024-12-25 15:43:50 +08:00
wjrforcyber 17652cfda6
Feat(write_hmetis): Write out hMetis file format 2024-12-25 15:37:36 +08:00
alanminko ef8230d9be
Merge pull request #353 from Carmine50/master 
cec: Modifying algorithm for generating simulation vectors for SAT sweeping (SimGen) and adding new feature to specify the simulation vector of the PIs for SAT sweeping algorithm.
 2024-12-24 11:36:05 -08:00
Carmine50 a74da1c50b [CEC][SAT Sweeping] Added new functionality in SAT sweeping function to use for simulation the PI vector present in vSimsPi data structure. 2024-12-24 14:54:59 +01:00
Carmine50 64e8bb02b9 [CEC][SimGen][Bits to Words] Changing the units of measure for random simulation from number bits to number words 2024-12-24 14:48:57 +01:00
Carmine50 5961231ed1 [CEC][SimGen][Clean codes] Disabling verbose. 2024-12-24 12:27:09 +01:00
Carmine50 7c6d1ffd2d [CEC][SimGen][Bugs] Fixing bugs and removing unused var. 2024-12-24 11:59:23 +01:00
Carmine50 37979dbd94 [CEC][SimGen][Clean codes] Removing commented SAT calls operations. 2024-12-24 11:50:47 +01:00
Carmine50 699c8c4c88 [CEC][SimGen][Clean codes] Removing commented SAT calls operations. 2024-12-24 11:50:11 +01:00
Carmine50 0ba2b7dae9 [CEC][SimGen][Clean codes] Removing unused parameters. 2024-12-24 11:49:17 +01:00
Carmine50 1a89f7ff63 [CEC][SimGen][CLI] Changed function name and help message. Added new option to specify file where to dump simulation vectors. Commented out too verbose information 2024-12-24 11:43:18 +01:00
Carmine50 463cf6a7df [CEC][SimGen][ABC Integration] Removed SAT solver calls and saving the simulation vectors in an internal data structure to pass to other functions. 2024-12-24 11:06:00 +01:00
Alan Mishchenko 14d46bfef8 Fixing big-endian problem if &fx and &deepsyn. 2024-12-23 20:26:00 -08:00
Alan Mishchenko 733fec328c Fixing big-endian problems in mfs2 and &mfs. 2024-12-23 20:04:21 -08:00
Alan Mishchenko cc894c5905 Deleting unused files. 2024-12-23 17:03:29 -08:00
Alan Mishchenko b81df1744f Removing unhelpful assertion. 2024-12-23 10:00:37 -08:00
Alan Mishchenko e21399f3bc Compiler warning. 2024-12-23 08:55:59 -08:00
alanminko 943bc0191c
Merge pull request #352 from wjrforcyber/conditional_jump 
Fix(&if -x): Conditional jump or move depends on uninitialised value(s)
 2024-12-23 08:52:54 -08:00
alanminko 01c6102ca7
Merge pull request #350 from wjrforcyber/put_bug_on_choice 
Fix(&put): &put bug with choices
 2024-12-23 08:52:29 -08:00
alanminko 733d2cd390
Merge pull request #348 from wjrforcyber/mem_leak 
Refactor(MemLeak): MemLeak fix in orchestrate
 2024-12-23 08:52:12 -08:00
wjrforcyber fdd66a8963
Fix(&if -x): Conditional jump or move depends on uninitialised value(s) 
From Valgrind:
==44570== Conditional jump or move depends on uninitialised value(s)
==44570==    at 0x9DEBA1: Dau_DsdRemoveBraces (dauMerge.c:563)
==44570==    by 0x9D1F53: Dau_DsdDecompose (dauDsd.c:1926)
==44570==    by 0x835523: If_DsdManCompute (ifDsd.c:2073)
==44570==    by 0x84177C: If_ObjPerformMappingAnd (ifMap.c:315)
==44570==    by 0x843720: If_ManPerformMappingRound (ifMap.c:667)
==44570==    by 0x813A01: If_ManPerformMappingComb (ifCore.c:126)
==44570==    by 0x813C88: If_ManPerformMapping (ifCore.c:91)
==44570==    by 0xE5F147: Gia_ManPerformMappingInt (giaIf.c:2503)
==44570==    by 0xE60976: Gia_ManPerformMapping (giaIf.c:2566)
==44570==    by 0x543605: Abc_CommandAbc9If (abc.c:41910)
==44570==    by 0x654739: CmdCommandDispatch (cmdUtils.c:157)
==44570==    by 0x64E0F2: Cmd_CommandExecute (cmdApi.c:210)
 2024-12-23 23:24:47 +08:00
Alan Mishchenko 42c2c54969 Fixing a big-endian issue in SOP manipulation and factoring. 2024-12-22 14:15:35 -08:00
Alan Mishchenko 207cfddaa8 Experiments with structural LUT cascade mapping. 2024-12-21 21:24:45 -08:00
Carmine50 ef8c35f95d [CEC][SimGen][LUT mapping] Adding option to consider an already mapped circuit before executing SimGen 2024-12-21 20:22:02 +01:00
Carmine50 8a1c28bf0f [CEC][SimGen][LUT mapping] Adding option to consider an already mapped circuit before executing SimGen 2024-12-21 20:15:40 +01:00
Carmine50 f407156de6 [CEC][SimGen][Warnings] Re-adjusted code to remove unused variables and avoid warnings compilation 2024-12-21 16:19:47 +01:00
Carmine50 bd80d2e459 [CEC][SimGen][Warnings] Re-adjusted code to remove unused variables and avoid warnings compilation 2024-12-21 16:04:45 +01:00
Carmine50 a6de82377d [CEC][SimGen][Warnings] Re-adjusted code to remove unused variables and avoid warnings compilation 2024-12-21 15:57:47 +01:00
Carmine50 c104d9cb72 [CEC][SimGen][Warnings] Re-adjusted code to remove unused variables and avoid warnings compilation 2024-12-21 14:26:54 +01:00
Carmine50 b999084ade [CEC][SimGen][CLI] Removed option of nMaxStep since it was unused 2024-12-19 18:12:28 +01:00
Carmine50 30af6f9868 [CEC][SimGen][CLI] Change name of command for simgen 2024-12-19 17:25:45 +01:00
Carmine50 87a3cafa44 [CEC][SimGen][Main Algo] Added main algorithm of SimGen and all necessary utility functions 2024-12-19 14:23:19 +01:00
Carmine50 0ea9929e65 [CEC][SimGen][Man new data struct] Added new variables in Gia_Man to save truth tables, MFFC infos and luts rankings for simgen. Modified also the function type to extract MFFC info 2024-12-19 14:22:26 +01:00
Carmine50 91dcfae020 [CEC][SimGen][Experiment ID] Added experiment ID option to test different experiments with simgen 2024-12-18 19:56:12 +01:00
Carmine50 cbd4456805 [CEC][SimGen][Experiment ID] Added experiment ID option to test different experiments with simgen 2024-12-18 19:53:44 +01:00
Carmine50 070ae52a46 [CEC][SimGen][Custom Parameters] Added custom parameters for SimGen CEC algo 2024-12-18 19:36:50 +01:00
Carmine50 99648e132f [CEC][SimGen][CLI] Added command line function to call SimGen main function. 2024-12-18 18:43:38 +01:00
wjrforcyber a8c65f1343
Fix(&put): &put bug with choices 
Related: #349
 2024-12-17 14:05:58 +08:00
Alan Mishchenko 8ba3d9b91c Trying anothe resource limit in scorr. 2024-12-14 13:44:18 -08:00
Alan Mishchenko 6754da13f2 Compiler warning. 2024-12-08 00:19:54 -08:00
wjrforcyber 7391a297bb
Refactor(MemLeak): MemLeak fix in orchestrate 2024-12-06 18:13:32 +08:00
Ethan Mahintorabi 01c9a65a47
map: Add Mio_Library_t* parameter to Abc_NtkMap 
This lets users of the ABC API call map without relying on the static
Mio_Library_t* in Abc_FrameReadLibGen.
 2024-12-02 06:55:42 +00:00
Alan Mishchenko 14168eb509 Updating command "rungen" to generate random functions. 2024-11-27 22:01:27 -08:00
Alan Mishchenko 1f3cf0aad9 Experiment with "scorr". 2024-11-17 15:44:32 -08:00
Alan Mishchenko 3aff0af0c5 Adding command for generating sorters. 2024-11-11 21:02:59 -08:00
Alan Mishchenko b5a76d8ba3 Compilation problem. 2024-11-10 19:30:24 -08:00
Alan Mishchenko f2e4ceb0e3 Update to "lutexact". 2024-11-10 19:12:40 -08:00
Alan Mishchenko aeb977286f Updates to LUT cascade synthesis. 2024-11-10 18:54:35 -08:00
Alan Mishchenko c787e32f86 Adding postiive minterm count for random functions generated by "lutexact". 2024-11-05 22:01:07 -08:00
Alan Mishchenko 091ff4e7a9 Adding generation of random functions to "lutexact" 2024-11-05 19:23:04 -08:00
Alan Mishchenko ecd948027e Fixing assertion failures in &put. 2024-10-23 14:49:57 +07:00
Alan Mishchenko cb2140dc0c Adding PI/PO name transfer after mapping+retiming. 2024-10-21 20:37:52 +07:00
alanminko 743f3a7bdd
Merge pull request #250 from wjrforcyber/typo 
Refactor(Typo):Typo currently exists
 2024-10-21 01:54:12 -07:00
alanminko 498ec539e6
Merge pull request #340 from aletempiac/acd_improvements 
Performance improvements to ACD
 2024-10-21 01:39:32 -07:00