mirror of https://github.com/YosysHQ/abc.git
Updates to rewiring.
This commit is contained in:
Alan Mishchenko
parent
f3ae349cf2
commit
7364002c39
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/**CFile****************************************************************
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FileName [rewire_map.c]
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SystemName [ABC: Logic synthesis and verification system.]
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PackageName [Re-wiring.]
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Synopsis []
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Author [Jiun-Hao Chen]
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Affiliation [National Taiwan University]
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Date [Ver. 1.0. Started - June 20, 2005.]
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Revision [$Id: rewire_map.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
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***********************************************************************/
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#include "rewire_map.h"
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ABC_NAMESPACE_IMPL_START
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/**CFile****************************************************************
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FileName [rewire_map.h]
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SystemName [ABC: Logic synthesis and verification system.]
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PackageName [Re-wiring.]
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Synopsis []
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Author [Jiun-Hao Chen]
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Affiliation [National Taiwan University]
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Date [Ver. 1.0. Started - June 20, 2005.]
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Revision [$Id: rewire_map.h,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
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***********************************************************************/
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#ifndef REWIRE_MAP_H
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#define REWIRE_MAP_H
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/**CFile****************************************************************
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FileName [rewire_miaig.cpp]
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SystemName [ABC: Logic synthesis and verification system.]
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PackageName [Re-wiring.]
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Synopsis []
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Author [Jiun-Hao Chen]
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Affiliation [National Taiwan University]
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Date [Ver. 1.0. Started - June 20, 2005.]
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Revision [$Id: rewire_miaig.cpp,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
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***********************************************************************/
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#include "rewire_rar.h"
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#include "rewire_miaig.h"
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/**CFile****************************************************************
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FileName [rewire_miaig.h]
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SystemName [ABC: Logic synthesis and verification system.]
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PackageName [Re-wiring.]
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Synopsis []
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Author [Jiun-Hao Chen]
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Affiliation [National Taiwan University]
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Date [Ver. 1.0. Started - June 20, 2005.]
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Revision [$Id: rewire_miaig.h,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
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***********************************************************************/
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#ifndef REWIRE_MIAIG_H
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#define REWIRE_MIAIG_H
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/**CFile****************************************************************
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FileName [rewire_rar.c]
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SystemName [ABC: Logic synthesis and verification system.]
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PackageName [Re-wiring.]
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Synopsis []
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Author [Jiun-Hao Chen]
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Affiliation [National Taiwan University]
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Date [Ver. 1.0. Started - June 20, 2005.]
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Revision [$Id: rewire_rar.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
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***********************************************************************/
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#include "rewire_rar.h"
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ABC_NAMESPACE_IMPL_START
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/**CFile****************************************************************
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FileName [rewire_rar.h]
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SystemName [ABC: Logic synthesis and verification system.]
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PackageName [Re-wiring.]
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Synopsis []
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Author [Jiun-Hao Chen]
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Affiliation [National Taiwan University]
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Date [Ver. 1.0. Started - June 20, 2005.]
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Revision [$Id: rewire_rar.h,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
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***********************************************************************/
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#ifndef RAR_H
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#define RAR_H
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/**CFile****************************************************************
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FileName [rewire_rng.c]
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SystemName [ABC: Logic synthesis and verification system.]
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PackageName [Re-wiring.]
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Synopsis []
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Author [Jiun-Hao Chen]
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Affiliation [National Taiwan University]
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Date [Ver. 1.0. Started - June 20, 2005.]
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Revision [$Id: rewire_rng.c,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
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***********************************************************************/
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#include "rewire_rng.h"
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ABC_NAMESPACE_IMPL_START
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/**CFile****************************************************************
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FileName [rewire_rng.h]
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SystemName [ABC: Logic synthesis and verification system.]
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PackageName [Re-wiring.]
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Synopsis []
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Author [Jiun-Hao Chen]
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Affiliation [National Taiwan University]
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Date [Ver. 1.0. Started - June 20, 2005.]
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Revision [$Id: rewire_rng.h,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
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***********************************************************************/
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#ifndef RAR_RNG_H
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#define RAR_RNG_H
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/**CFile****************************************************************
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FileName [rewire_time.h]
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SystemName [ABC: Logic synthesis and verification system.]
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PackageName [Re-wiring.]
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Synopsis []
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Author [Jiun-Hao Chen]
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Affiliation [National Taiwan University]
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Date [Ver. 1.0. Started - June 20, 2005.]
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Revision [$Id: rewire_time.h,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
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***********************************************************************/
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#ifndef RAR_TIME_H
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#define RAR_TIME_H
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/**CFile****************************************************************
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FileName [rewire_tt.h]
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SystemName [ABC: Logic synthesis and verification system.]
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PackageName [Re-wiring.]
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Synopsis []
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Author [Jiun-Hao Chen]
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Affiliation [National Taiwan University]
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Date [Ver. 1.0. Started - June 20, 2005.]
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Revision [$Id: rewire_tt.h,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
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***********************************************************************/
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#ifndef RAR_TT_H
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#define RAR_TT_H
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/**CFile****************************************************************
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FileName [rewire_vec.h]
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SystemName [ABC: Logic synthesis and verification system.]
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PackageName [Re-wiring.]
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Synopsis []
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Author [Jiun-Hao Chen]
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Affiliation [National Taiwan University]
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Date [Ver. 1.0. Started - June 20, 2005.]
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Revision [$Id: rewire_vec.h,v 1.00 2005/06/20 00:00:00 alanmi Exp $]
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***********************************************************************/
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#ifndef RAR_VI_H
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#define RAR_VI_H
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