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807 Commits

Author SHA1 Message Date
Alan Mishchenko ba64e78608 Changing declaration of Vec_Ptr_t sorting function to satisfy some compilers. 2021-09-26 11:30:54 -07:00
Alan Mishchenko 787dbb9433 Two rare corner-case bugs in &if mapper. 2021-09-26 11:05:48 -07:00
Alan Mishchenko 9fac6c7a8b Experiments with CEC. 2021-07-10 10:50:33 -07:00
Alan Mishchenko 96b9192c78 Experiments with MUX decomposition. 2021-07-08 21:54:07 -07:00
Alan Mishchenko 8889ccb18c Updating LUT synthesis code. 2021-05-26 23:25:08 -07:00
Alan Mishchenko 9b75906740 Several changes for standard mapping. 2021-04-28 00:11:02 -07:00
Alan Mishchenko e463930709 Updating the mapper when user-specific matching is used. 2021-01-09 18:39:37 -08:00
Alan Mishchenko 73f8b598ac Rare bug fix in mapping with choices. 2020-10-29 17:21:37 -07:00
Alan Mishchenko e149cdcd77 Compiler warnings. 2020-05-03 12:15:54 -07:00
Alan Mishchenko 2b58a83ac0 Adding dumping of genlib library in Verilog. 2020-05-03 12:11:48 -07:00
Alan Mishchenko 559f8f5b5e Adding dumping of genlib library in Verilog. 2020-05-03 12:09:55 -07:00
Alan Mishchenko 3e150dd553 Adding dumping of genlib library in Verilog. 2020-05-03 12:07:52 -07:00
Alan Mishchenko dccd399255 Adding dynamic memory alloc for the buffer in Liberty file reader. 2020-01-11 07:12:48 +02:00
Alan Mishchenko f6dc4a588c Making sure arrival time of constant node is -infinity. 2020-01-02 17:58:05 -05:00
Alan Mishchenko feb3e7943d Adding limit on the depth of recursion when counting exact area in 'amap'. 2019-10-26 16:29:05 +03:00
Alan Mishchenko 3b4e9573bc Small bug in the unused code. 2019-10-04 10:47:46 -07:00
Alan Mishchenko b292595062 Adding switch to &if to consider special type of 6-input cuts. 2019-09-26 14:05:16 -07:00
Alan Mishchenko 390adc39ca Making &mfs work with boxes larger than 6 inputs. Adding option &if -w to print delay profile. 2019-09-19 16:49:36 -07:00
Alan Mishchenko ee1bd8f0be Fixing some update gcc. 2019-07-24 11:44:28 +07:00
Alan Mishchenko 62487de97b Adding support for user-specified wire delays in &if. 2019-05-29 14:46:25 -07:00
Alan Mishchenko f0efc6e098 Prevent assertions from firing for deep logic networks. 2019-03-20 22:07:27 +02:00
Alan Mishchenko 01569b8f5f Fixing some warnings by adding cast from 'int' to 'size_t' in memset, memcpy, etc. 2019-03-05 15:57:50 -08:00
Alan Mishchenko b632c8496c Fixing some warnings with -Wconversion. 2019-03-05 15:07:10 -08:00
Alan Mishchenko 1f016988b2 Fixing float overflow during edge-flow computation in 'if' mapper (change to avoid dependence on the order of additions). 2018-12-12 22:15:10 -08:00
Alan Mishchenko 2f88284d7b Fixing float overflow during edge-flow computation in 'if' mapper. 2018-12-12 10:47:53 -08:00
Alan Mishchenko 5aa3025ce7 Adding switch &w -n to modify the comment section of the AIGER file written. 2018-11-21 13:12:01 -08:00
Alan Mishchenko 18943f6462 Skip cells in Liberty files which have dont_use attribute. 2018-10-18 17:09:23 +07:00
Alan Mishchenko d05fe039e1 Suggested bug fix in 'amap'. 2018-09-13 11:47:38 +03:00
Alan Mishchenko 7e9f3f027b Adding parameters and improvements to %blast. 2018-02-28 18:45:44 -08:00
Alan Mishchenko 76b00a2d3e Compilation problem with pow(). 2018-02-19 09:07:44 -08:00
Staf Verhaegen e4875df4e5 Value of properties can be expression. 
Example found in the 2007.03 Liberty Reference Manual that was also found
in the wild:

    input_voltage(CMOS) {
        vil : 0.3 * VDD ;
        vih : 0.7 * VDD ;
        vimin : -0.5 ;
        vimax : VDD + 0.5 ;
    }

Current implementation just parses the expression but no interpretation is done.
 2018-01-03 21:54:38 +00:00
Alan Mishchenko accf4825e5 Adding API to dump MiniAIG into a Verilog file and other small changes. 2017-10-22 15:44:13 -07:00
Alan Mishchenko 1e1d41f3b8 Fix typo on the message reporting max output load. 2017-10-11 18:14:03 +07:00
Alan Mishchenko 396215532c Updates and bug fixes. 2017-10-04 12:37:38 +03:00
Alan Mishchenko c696ae95d0 Maintenance and updates. 2017-09-24 23:38:01 -07:00
Alan Mishchenko 287f9efcce Maintenance and updates. 2017-09-20 19:27:46 -07:00
Alan Mishchenko 3a1032c151 Maintenance and updates. 2017-09-18 08:27:05 -07:00
Alan Mishchenko 2e56f44c66 Compiler warnings. 2017-07-22 11:41:17 +07:00
Alan Mishchenko 859e769f22 Synchronizing various data-structures. 2017-07-04 15:23:51 -07:00
Alan Mishchenko bf6a053c64 Saturating floating point computation. 2017-07-01 13:48:31 -07:00
Alan Mishchenko a1dd7e3fb0 Saturating floating point computation. 2017-06-29 17:58:43 -07:00
Alan Mishchenko d92bfbaddc Experiments with new network data-structure. 2017-03-20 23:45:03 -07:00
Alan Mishchenko 19ccaf21df Experiments with new network data-structure. 2017-03-19 21:51:03 -07:00
Heinz Riener a20002dab1 stringizing macro argument 2017-03-03 12:03:55 +01:00
Alan Mishchenko 7d5b1c572b Restoring constraint manager to read old constraint file by default (use 'read_constr -n' to read new format). 2017-02-25 13:34:54 -08:00
Alan Mishchenko afcbb09717 Corner-case bug-fix in library preprocessor for standard-cell mapping. 2017-02-05 10:43:07 -08:00
Alan Mishchenko dc7445e435 Typo. 2017-01-31 11:09:38 -08:00
Alan Mishchenko 8ad3d6bec8 Bug fixes by Clifford Wolf. 2017-01-08 03:10:42 +07:00
Alan Mishchenko 460167ec74 Compiler warnings. 2017-01-07 08:57:08 +07:00
Alan Mishchenko 3f2899d6ea Compiler warnings. 2016-12-31 22:00:26 +07:00
Alan Mishchenko d9fdd10960 Bug fix in Liberty parser. 2016-12-05 19:54:17 -08:00
Alan Mishchenko c6afb9db63 Equivalent fault detection code. 2016-11-09 21:17:44 -08:00
Alan Mishchenko 710f5cd4bc Memory leak in scl package. 2016-10-12 11:59:32 -07:00
Alan Mishchenko 693b587c5c Adding truth table occurrence counters for 'if -c'. 2016-08-08 18:20:05 -07:00
Alan Mishchenko 713976f2cf Enabled progress bar in the 'if' mapper (warning). 2016-08-08 12:38:21 -07:00
Alan Mishchenko a819e33c6f Enabled delay computation for the cut output using cut inputs. 2016-08-08 12:36:10 -07:00
Alan Mishchenko 473012aaf0 Enabled progress bar in the 'if' mapper. 2016-08-08 11:56:33 -07:00
Alan Mishchenko fd8eb8c855 Adding one argument to the delay-estimation API used for exact synthesis. 2016-07-31 13:31:57 -07:00
Alan Mishchenko cf91699e05 Infrastructure for using the results of exact SAT-based synthesis during mapping. 2016-07-29 16:34:47 -07:00
Alan Mishchenko fb33d69db8 Infrastructure for using the results of exact SAT-based synthesis during mapping. 2016-07-29 16:03:42 -07:00
Alan Mishchenko db43d6fbd8 Adding switch -P <num> to command 'cover'. 2016-06-14 20:43:50 -07:00
Alan Mishchenko 07d074fd88 New feature for area minimization in standard cell mapping. 2016-05-19 15:22:25 -07:00
Alan Mishchenko 7c089a3ac6 Factoring out library preprocessing code in &nf and putting it elsewhere. 2016-05-16 16:50:01 -07:00
Alan Mishchenko 20a2b0a0f2 Added switch 'read_genlib -n' to anonymize Genlib library. 2016-05-16 15:44:54 -07:00
Alan Mishchenko 53e8647719 Adding option to rehash AIG after mapping. 2016-04-27 18:33:23 -07:00
Alan Mishchenko 22a5ab19c8 Adding API to convert Genlib into a simple Liberty. 2016-03-11 00:15:13 +09:00
Alan Mishchenko 5a47990043 Disabling formula cleaner to avoid problems with reading GENLIB on some libraries. 2016-02-21 18:15:05 -08:00
Alan Mishchenko 59aea7639f Bug fix in liberty parser and change suggested by Clifford. 2016-02-07 12:54:13 -08:00
Alan Mishchenko 355865e81b GENLIB parsing bug, which led to a crash. 2016-02-06 12:07:42 -08:00
Alan Mishchenko 367b20f04d Fixing mismatch in the TLS flow induced by adding cell configs in the DSD manager. 2016-01-30 20:59:57 -08:00
Alan Mishchenko 87f6828d50 Adding support for delay/area tradeoff. 2016-01-13 12:13:54 -08:00
Alan Mishchenko a4f9776388 Consolidating timing manager Scl_Con_t and propagating changes. 2016-01-07 16:50:01 -08:00
Alan Mishchenko 15a891f97a Bug fix in constraint file reader. 2016-01-07 11:57:16 -08:00
Alan Mishchenko c158dd5a94 Migrating to using 32-bit timing representation in &nf. 2016-01-05 16:40:00 -08:00
Alan Mishchenko 19ad75f125 Migrating back to using 'float' in area-flow computation in &nf. 2016-01-05 14:05:07 -08:00
Alan Mishchenko 6642e40af5 Corner-case bug in 'read_profile'. 2015-12-22 22:09:25 -10:00
Alan Mishchenko 19586f105c Adding code to support gate profiles. 2015-12-14 00:44:33 -08:00
Alan Mishchenko e9abb0f489 Adding code to support gate profiles. 2015-12-07 01:31:41 -08:00
Alan Mishchenko 0f29ba75f6 Adding commands to read/write/print gate profiles. 2015-12-05 18:10:43 -08:00
Alan Mishchenko f7c969ca66 Improvements to timing optimization. 2015-11-11 23:12:05 -08:00
Alan Mishchenko 3c9f7d2bc8 Extending and improving timing manager. 2015-11-08 19:59:34 -08:00
Alan Mishchenko efb8ad0af8 Extending and improving timing manager. 2015-11-08 12:08:50 -08:00
Alan Mishchenko 96d8f899d9 Extending and improving timing manager. 2015-11-08 11:44:37 -08:00
Baruch Sterin c0ba25a693 silence clang errors when compiling as C++ 2015-11-05 01:23:31 -08:00
Alan Mishchenko 8ee49ff150 Bug fix in constructing internal choices by 'amap'. 2015-11-04 15:15:18 -08:00
Alan Mishchenko 35143e830b Experiments with precomputation and matching. 2015-10-27 10:48:40 -07:00
Alan Mishchenko bd586dd355 Changes for delay-oriented computation. 2015-10-26 16:44:04 -07:00
Alan Mishchenko 9519341aaf Extending library handling to 8 inputs. 2015-10-25 20:23:44 -07:00
Alan Mishchenko 61d4623207 Adding switch in 'print_genlib' and 'write_genlib' to print area-min gates only. 2015-10-23 17:17:23 -07:00
Alan Mishchenko 3712dd30d0 Changes for delay-oriented computation. 2015-10-23 15:14:31 -07:00
Alan Mishchenko 2c37498bfb Compiler warnings. 2015-10-21 23:53:42 -07:00
Alan Mishchenko 0145b0ca72 Moving BDD-based threshold function detection to the BDD part of the code. 2015-10-16 18:34:06 -07:00
Alan Mishchenko 15a86aefd2 Experiments with precomputation and matching. 2015-10-15 15:32:36 -07:00
Alan Mishchenko 20c46b5a45 Experiments with precomputation and matching. 2015-10-12 18:29:15 -07:00
Alan Mishchenko 46223f903b Two fixes in 'dsd_filter'. 2015-10-07 17:48:07 -07:00
Alan Mishchenko b19d09f04c Bug fix in 'if -g' (incorrect use of a macro). 2015-10-07 08:37:25 -07:00
Alan Mishchenko 78951b4c6f Improvements to Scl_Lib/SC_Cell data-structure. 2015-09-24 12:12:36 -07:00
Alan Mishchenko f1bc346894 Several bug-fixed related to synthesis, library handling, and timimg info. 2015-09-23 18:44:07 -07:00
Alan Mishchenko 19a4bb930e Threshold logic checking code by Augusto Neutzling and Jody Matos. 2015-09-23 15:24:25 -07:00
Alan Mishchenko 97751e43b7 New constraint manager and memory reporting 'ps'. 2015-09-08 19:53:49 -07:00