mirror of https://github.com/YosysHQ/abc.git
Factoring out library preprocessing code in &nf and putting it elsewhere.
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20a2b0a0f2
commit
7c089a3ac6
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@ -178,18 +178,17 @@ int Nf_StoCellIsDominated( Mio_Cell2_t * pCell, int * pFans, int * pProf )
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return 0;
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return 1; // pCell is dominated
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}
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void Nf_StoCreateGateAdd( Nf_Man_t * pMan, word uTruth, int * pFans, int nFans, int CellId, Vec_Wec_t * vProfs, Vec_Int_t * vStore )
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void Nf_StoCreateGateAdd( Vec_Mem_t * vTtMem, Vec_Wec_t * vTt2Match, Mio_Cell2_t * pCell, word uTruth, int * pFans, int nFans, Vec_Wec_t * vProfs, Vec_Int_t * vStore, int fPinFilter, int fPinPerm, int fPinQuick )
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{
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Vec_Int_t * vArray, * vArrayProfs = NULL;
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Mio_Cell2_t * pCell = Nf_ManCell( pMan, CellId );
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int i, k, GateId, Entry, fCompl = (int)(uTruth & 1);
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word uFunc = fCompl ? ~uTruth : uTruth;
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int iFunc = Vec_MemHashInsert( pMan->vTtMem, &uFunc );
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int iFunc = Vec_MemHashInsert( vTtMem, &uFunc );
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Nf_Cfg_t Mat = Nf_Int2Cfg(0);
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// get match array
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if ( iFunc == Vec_WecSize(pMan->vTt2Match) )
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Vec_WecPushLevel( pMan->vTt2Match );
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vArray = Vec_WecEntry( pMan->vTt2Match, iFunc );
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if ( iFunc == Vec_WecSize(vTt2Match) )
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Vec_WecPushLevel( vTt2Match );
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vArray = Vec_WecEntry( vTt2Match, iFunc );
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// create match
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Mat.fCompl = fCompl;
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assert( nFans == (int)pCell->nFanins );
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@ -199,10 +198,10 @@ void Nf_StoCreateGateAdd( Nf_Man_t * pMan, word uTruth, int * pFans, int nFans,
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Mat.Phase |= (unsigned)(Abc_LitIsCompl(pFans[i]) << Abc_Lit2Var(pFans[i]));
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}
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// check other profiles
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if ( pMan->pPars->fPinFilter )
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if ( fPinFilter )
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{
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// get profile array
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assert( Vec_WecSize(pMan->vTt2Match) == Vec_WecSize(vProfs) );
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assert( Vec_WecSize(vTt2Match) == Vec_WecSize(vProfs) );
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if ( iFunc == Vec_WecSize(vProfs) )
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Vec_WecPushLevel( vProfs );
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vArrayProfs = Vec_WecEntry( vProfs, iFunc );
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@ -218,26 +217,26 @@ void Nf_StoCreateGateAdd( Nf_Man_t * pMan, word uTruth, int * pFans, int nFans,
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}
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}
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// check pin permutation
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if ( !pMan->pPars->fPinPerm ) // do not use pin-permutation (improves delay when pin-delays differ)
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if ( !fPinPerm ) // do not use pin-permutation (improves delay when pin-delays differ)
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{
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if ( pMan->pPars->fPinQuick ) // reduce the number of matches agressively
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if ( fPinQuick ) // reduce the number of matches agressively
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{
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Vec_IntForEachEntryDouble( vArray, GateId, Entry, i )
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if ( GateId == CellId && Abc_TtBitCount8[Nf_Int2Cfg(Entry).Phase] == Abc_TtBitCount8[Mat.Phase] )
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if ( GateId == (int)pCell->Id && Abc_TtBitCount8[Nf_Int2Cfg(Entry).Phase] == Abc_TtBitCount8[Mat.Phase] )
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return;
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}
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else // reduce the number of matches less agressively
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{
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Vec_IntForEachEntryDouble( vArray, GateId, Entry, i )
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if ( GateId == CellId && Nf_Int2Cfg(Entry).Phase == Mat.Phase )
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if ( GateId == (int)pCell->Id && Nf_Int2Cfg(Entry).Phase == Mat.Phase )
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return;
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}
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}
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// save data and profile
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Vec_IntPush( vArray, CellId );
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Vec_IntPush( vArray, pCell->Id );
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Vec_IntPush( vArray, Nf_Cfg2Int(Mat) );
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// add delay profile
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if ( pMan->pPars->fPinFilter )
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if ( fPinFilter )
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{
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Vec_IntPush( vArrayProfs, Vec_IntSize(vStore) );
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Vec_IntPush( vStore, Abc_Float2Int(pCell->AreaF) );
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@ -245,7 +244,7 @@ void Nf_StoCreateGateAdd( Nf_Man_t * pMan, word uTruth, int * pFans, int nFans,
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Vec_IntPush( vStore, pCell->iDelays[Abc_Lit2Var(pFans[k])] );
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}
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}
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void Nf_StoCreateGateMaches( Nf_Man_t * pMan, Mio_Cell2_t * pCell, int ** pComp, int ** pPerm, int * pnPerms, Vec_Wec_t * vProfs, Vec_Int_t * vStore )
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void Nf_StoCreateGateMaches( Vec_Mem_t * vTtMem, Vec_Wec_t * vTt2Match, Mio_Cell2_t * pCell, int ** pComp, int ** pPerm, int * pnPerms, Vec_Wec_t * vProfs, Vec_Int_t * vStore, int fPinFilter, int fPinPerm, int fPinQuick )
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{
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int Perm[NF_LEAF_MAX], * Perm1, * Perm2;
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int nPerms = pnPerms[pCell->nFanins];
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@ -261,7 +260,7 @@ void Nf_StoCreateGateMaches( Nf_Man_t * pMan, Mio_Cell2_t * pCell, int ** pComp,
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tTemp2 = tCur;
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for ( c = 0; c < nMints; c++ )
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{
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Nf_StoCreateGateAdd( pMan, tCur, Perm, pCell->nFanins, pCell->Id, vProfs, vStore );
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Nf_StoCreateGateAdd( vTtMem, vTt2Match, pCell, tCur, Perm, pCell->nFanins, vProfs, vStore, fPinFilter, fPinPerm, fPinQuick );
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// update
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tCur = Abc_Tt6Flip( tCur, pComp[pCell->nFanins][c] );
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Perm1 = Perm + pComp[pCell->nFanins][c];
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@ -278,12 +277,14 @@ void Nf_StoCreateGateMaches( Nf_Man_t * pMan, Mio_Cell2_t * pCell, int ** pComp,
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}
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assert( tTemp1 == tCur );
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}
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void Nf_StoDeriveMatches( Nf_Man_t * p, int fVerbose )
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Mio_Cell2_t * Nf_StoDeriveMatches( Vec_Mem_t * vTtMem, Vec_Wec_t * vTt2Match, int * pnCells, int fPinFilter, int fPinPerm, int fPinQuick )
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{
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// abctime clk = Abc_Clock();
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int fVerbose = 0;
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//abctime clk = Abc_Clock();
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Vec_Wec_t * vProfs = Vec_WecAlloc( 1000 );
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Vec_Int_t * vStore = Vec_IntAlloc( 10000 );
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int * pComp[7], * pPerm[7], nPerms[7], i;
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Mio_Cell2_t * pCells;
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Vec_WecPushLevel( vProfs );
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Vec_WecPushLevel( vProfs );
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for ( i = 1; i <= 6; i++ )
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@ -292,18 +293,18 @@ void Nf_StoDeriveMatches( Nf_Man_t * p, int fVerbose )
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pPerm[i] = Extra_PermSchedule( i );
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for ( i = 1; i <= 6; i++ )
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nPerms[i] = Extra_Factorial( i );
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p->pCells = Mio_CollectRootsNewDefault2( 6, &p->nCells, fVerbose );
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for ( i = 2; i < p->nCells; i++ )
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Nf_StoCreateGateMaches( p, p->pCells + i, pComp, pPerm, nPerms, vProfs, vStore );
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pCells = Mio_CollectRootsNewDefault2( 6, pnCells, fVerbose );
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for ( i = 2; i < *pnCells; i++ )
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Nf_StoCreateGateMaches( vTtMem, vTt2Match, pCells+i, pComp, pPerm, nPerms, vProfs, vStore, fPinFilter, fPinPerm, fPinQuick );
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for ( i = 1; i <= 6; i++ )
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ABC_FREE( pComp[i] );
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for ( i = 1; i <= 6; i++ )
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ABC_FREE( pPerm[i] );
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Vec_WecFree( vProfs );
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Vec_IntFree( vStore );
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// Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
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//Abc_PrintTime( 1, "Time", Abc_Clock() - clk );
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return pCells;
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}
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//void Nf_StoPrintOne( Nf_Man_t * p, int Count, int t, int i, int GateId, Pf_Mat_t Mat )
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void Nf_StoPrintOne( Nf_Man_t * p, int Count, int t, int i, int GateId, Nf_Cfg_t Mat )
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{
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Mio_Cell2_t * pC = p->pCells + GateId;
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@ -398,12 +399,7 @@ Nf_Man_t * Nf_StoCreate( Gia_Man_t * pGia, Jf_Par_t * pPars )
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}
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Vec_IntFree(vFlowRefs);
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// matching
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p->vTtMem = Vec_MemAllocForTT( 6, 0 );
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p->vTt2Match = Vec_WecAlloc( 1000 );
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Vec_WecPushLevel( p->vTt2Match );
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Vec_WecPushLevel( p->vTt2Match );
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assert( Vec_WecSize(p->vTt2Match) == Vec_MemEntryNum(p->vTtMem) );
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Nf_StoDeriveMatches( p, 0 );//pPars->fVerbose );
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Mio_LibraryMatchesFetch( (Mio_Library_t *)Abc_FrameReadLibGen(), &p->vTtMem, &p->vTt2Match, &p->pCells, &p->nCells, p->pPars->fPinFilter, p->pPars->fPinPerm, p->pPars->fPinQuick );
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p->InvDelayI = p->pCells[3].iDelays[0];
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p->InvAreaW = p->pCells[3].AreaW;
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p->InvAreaF = p->pCells[3].AreaF;
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@ -424,11 +420,6 @@ void Nf_StoDelete( Nf_Man_t * p )
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ABC_FREE( p->vCutDelays.pArray );
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ABC_FREE( p->vBackup.pArray );
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ABC_FREE( p->pNfObjs );
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// matching
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Vec_WecFree( p->vTt2Match );
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Vec_MemHashFree( p->vTtMem );
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Vec_MemFree( p->vTtMem );
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ABC_FREE( p->pCells );
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ABC_FREE( p );
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}
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@ -215,6 +215,10 @@ extern int Mio_LibraryHasProfile( Mio_Library_t * pLib );
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extern void Mio_LibraryCleanProfile2( Mio_Library_t * pLib );
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extern void Mio_LibraryShortNames( Mio_Library_t * pLib );
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extern void Mio_LibraryMatchesStop( Mio_Library_t * pLib );
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extern void Mio_LibraryMatchesStart( Mio_Library_t * pLib, int fPinFilter, int fPinPerm, int fPinQuick );
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extern void Mio_LibraryMatchesFetch( Mio_Library_t * pLib, Vec_Mem_t ** pvTtMem, Vec_Wec_t ** pvTt2Match, Mio_Cell2_t ** ppCells, int * pnCells, int fPinFilter, int fPinPerm, int fPinQuick );
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/*=== sclUtil.c =========================================================*/
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extern Mio_Library_t * Abc_SclDeriveGenlibSimple( void * pScl );
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extern Mio_Library_t * Abc_SclDeriveGenlib( void * pScl, void * pMio, float Slew, float Gain, int nGatesMin, int fVerbose );
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@ -76,6 +76,14 @@ struct Mio_LibraryStruct_t_
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st__table * tName2Gate; // the mapping of gate names into their pointer
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Mem_Flex_t * pMmFlex; // the memory manaqer for SOPs
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Vec_Str_t * vCube; // temporary cube
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// matching
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int fPinFilter; // pin filtering
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int fPinPerm; // pin permutation
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int fPinQuick; // pin permutation
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Vec_Mem_t * vTtMem; // truth tables
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Vec_Wec_t * vTt2Match; // matches for truth tables
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Mio_Cell2_t * pCells; // library gates
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int nCells; // library gate count
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};
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struct Mio_GateStruct_t_
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@ -53,6 +53,7 @@ void Mio_LibraryDelete( Mio_Library_t * pLib )
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Mio_Gate_t * pGate, * pGate2;
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if ( pLib == NULL )
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return;
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Mio_LibraryMatchesStop( pLib );
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// free the bindings of nodes to gates from this library for all networks
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Abc_FrameUnmapAllNetworks( Abc_FrameGetGlobalFrame() );
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// free the library
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@ -1590,6 +1591,52 @@ void Mio_LibraryShortNames( Mio_Library_t * pLib )
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pLib->pName = Abc_UtilStrsav( Buffer );
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}
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/**Function*************************************************************
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Synopsis []
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Description []
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SideEffects []
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SeeAlso []
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***********************************************************************/
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void Mio_LibraryMatchesStop( Mio_Library_t * pLib )
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{
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if ( !pLib->vTtMem )
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return;
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Vec_WecFree( pLib->vTt2Match );
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Vec_MemHashFree( pLib->vTtMem );
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Vec_MemFree( pLib->vTtMem );
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ABC_FREE( pLib->pCells );
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}
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void Mio_LibraryMatchesStart( Mio_Library_t * pLib, int fPinFilter, int fPinPerm, int fPinQuick )
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{
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extern Mio_Cell2_t * Nf_StoDeriveMatches( Vec_Mem_t * vTtMem, Vec_Wec_t * vTt2Match, int * pnCells, int fPinFilter, int fPinPerm, int fPinQuick );
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if ( pLib->vTtMem && pLib->fPinFilter == fPinFilter && pLib->fPinPerm == fPinPerm && pLib->fPinQuick == fPinQuick )
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return;
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if ( pLib->vTtMem )
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Mio_LibraryMatchesStop( pLib );
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pLib->fPinFilter = fPinFilter; // pin filtering
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pLib->fPinPerm = fPinPerm; // pin permutation
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pLib->fPinQuick = fPinQuick; // pin permutation
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pLib->vTtMem = Vec_MemAllocForTT( 6, 0 );
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pLib->vTt2Match = Vec_WecAlloc( 1000 );
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Vec_WecPushLevel( pLib->vTt2Match );
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Vec_WecPushLevel( pLib->vTt2Match );
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assert( Vec_WecSize(pLib->vTt2Match) == Vec_MemEntryNum(pLib->vTtMem) );
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pLib->pCells = Nf_StoDeriveMatches( pLib->vTtMem, pLib->vTt2Match, &pLib->nCells, fPinFilter, fPinPerm, fPinQuick );
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}
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void Mio_LibraryMatchesFetch( Mio_Library_t * pLib, Vec_Mem_t ** pvTtMem, Vec_Wec_t ** pvTt2Match, Mio_Cell2_t ** ppCells, int * pnCells, int fPinFilter, int fPinPerm, int fPinQuick )
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{
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Mio_LibraryMatchesStart( pLib, fPinFilter, fPinPerm, fPinQuick );
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*pvTtMem = pLib->vTtMem; // truth tables
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*pvTt2Match = pLib->vTt2Match; // matches for truth tables
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*ppCells = pLib->pCells; // library gates
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*pnCells = pLib->nCells; // library gate count
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}
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////////////////////////////////////////////////////////////////////////
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/// END OF FILE ///
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////////////////////////////////////////////////////////////////////////
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@ -36,6 +36,8 @@
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#include "vecAtt.h"
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#include "vecWrd.h"
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#include "vecBit.h"
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#include "vecMem.h"
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#include "vecWec.h"
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////////////////////////////////////////////////////////////////////////
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/// MACRO DEFINITIONS ///
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